Speed and power

You know a MOSFET is a voltage-controlled switch. To predict how fast and how hungry a circuit built from it will be, you need three more pieces: how much current the switch carries when on, how much it leaks when off, and how much capacitance it must charge. This chapter turns those into four working models:

1. Delay: an RC charging model, refined with the alpha-power law so that delay depends on $V_{\mathrm{DD}}$ and $V_{\mathrm{T}}$ the way real short-channel devices do.
2. Switching power: $P = \alpha C V_{\mathrm{DD}}^2 f$, and where the energy actually goes.
3. Leakage: subthreshold conduction, exponential in $-V_{\mathrm{T}}/(n\,kT/q)$, plus gate tunneling.
4. The $V_{\mathrm{DD}}/V_{\mathrm{T}}$ trade: why the two voltages have to be chosen together, how multi-threshold libraries let a design use different points on the curve in different places, and where energy per operation bottoms out.

Then the history that explains the present: Dennard’s 1974 scaling rules, which kept power density constant as transistors shrank, and why they broke when threshold voltage hit a floor set by thermodynamics rather than by lithography.¹

The RC model

Treat the switching transistor as an effective resistance $R_{\mathrm{eff}}$ charging the load $C_{\mathrm{L}}$. The step response of an RC node crosses 50% at $t = \ln 2 \cdot RC \approx 0.69\,RC$, so to first order $t_{\mathrm{pd}} \approx 0.69\,R_{\mathrm{eff}} C_{\mathrm{L}}$. For a chain or tree of RC segments the Elmore delay, the sum over each resistor of $R_{i}$ times all the capacitance downstream of it, generalizes this.² $R_{\mathrm{eff}}$ scales as $1/W$ (transistor width), and $C_{\mathrm{L}} = C_{\mathrm{wire}} + \sum C_{\mathrm{in}} + C_{\mathrm{self}}$, where each driven gate’s input capacitance also scales with its width. That coupling is why sizing is an optimization rather than “make everything wide.” A common process-independent unit for the result is the FO4 delay: an inverter driving four copies of itself.

Putting the voltages in

$R_{\mathrm{eff}}$ hides the voltage dependence. A more useful first-order form treats the transistor as a current source discharging the load: the time to move the output by $V_{\mathrm{DD}}/2$ is

and everything interesting is in $I_{\mathrm{on}}$. The long-channel square law gives $I_{\mathrm{on}} \propto (V_{\mathrm{DD}} - V_{\mathrm{T}})^2$. Short-channel devices don’t follow it: once the lateral field is high enough, carrier velocity saturates and current grows more slowly with overdrive (see The I-V curve). Sakurai and Newton’s alpha-power law captures this with one fitted exponent:

$\alpha = 2$ recovers the square law, and $\alpha$ falls toward 1 as velocity saturation gets more severe: Sakurai and Newton note that measured short-channel $I_{\mathrm{D}}$–$V_{\mathrm{GS}}$ curves are close to linear. Their closed-form inverter delay is a term proportional to the input transition time plus $C_{\mathrm{L}} V_{\mathrm{DD}}/(2 I_{\mathrm{D0}})$, where $I_{\mathrm{D0}}$ is the drain current at $V_{\mathrm{GS}} = V_{\mathrm{DS}} = V_{\mathrm{DD}}$. With $I_{\mathrm{D0}} \propto (V_{\mathrm{DD}} - V_{\mathrm{T}})^{\alpha}$, delay goes as $V_{\mathrm{DD}}/(V_{\mathrm{DD}} - V_{\mathrm{T}})^{\alpha}$.³ Fitted values for modern processes land in between; Harris quotes $\alpha \approx 1.3$ for a 65 nm process.⁴

Step by step, with $\alpha = 1.3$ and $V_{\mathrm{T}} = 0.3\,\mathrm{V}$ (delay in arbitrary units, $V_{\mathrm{DD}}/(V_{\mathrm{DD}} - V_{\mathrm{T}})^{1.3}$):

• $V_{\mathrm{DD}} = 1.0\,\mathrm{V}$: $1.0/0.7^{1.3} = 1.0/0.629 = 1.59$.
• $V_{\mathrm{DD}} = 0.7\,\mathrm{V}$: $0.7/0.4^{1.3} = 0.7/0.304 = 2.30$. That is 45% slower, for a 51% cut in switching energy ($0.7^2 = 0.49$).
• $V_{\mathrm{DD}} = 0.5\,\mathrm{V}$: 2.5× slower than at 1.0 V. At 0.4 V: 5× slower. The curve turns sharply upward as the overdrive vanishes.
• Lowering $V_{\mathrm{T}}$ from 0.3 V to 0.2 V cuts delay by 25% at $V_{\mathrm{DD}} = 0.7\,\mathrm{V}$ but only 16% at 1.0 V. Threshold matters most when the supply is low.

Below $V_{\mathrm{T}}$ the alpha-power law no longer applies. The transistor conducts only by diffusion, current is exponential in $V_{\mathrm{GS}}$, and so is delay. That regime is where the minimum-energy story in “Under the hood” plays out.

Real libraries don’t evaluate formulas. They characterize every cell in circuit simulation over a grid of input slews and output loads and store the delays in tables, one set per process, voltage and temperature corner (see From devices to a cell library). The models here are for intuition and early estimates.

Where the energy goes

During a 0→1 transition the supply delivers $\int V_{\mathrm{DD}}\, i\, dt = V_{\mathrm{DD}} Q = C_{\mathrm{L}} V_{\mathrm{DD}}^2$. The capacitor ends with $\tfrac{1}{2} C_{\mathrm{L}} V_{\mathrm{DD}}^2$; the other half is dissipated in the pull-up network’s resistance, independent of that resistance’s value. On 1→0 the stored $\tfrac{1}{2} C_{\mathrm{L}} V_{\mathrm{DD}}^2$ is dissipated in the pull-down, and the supply delivers nothing. So the energy per complete cycle is $C_{\mathrm{L}} V_{\mathrm{DD}}^2$, and transistor sizing or switching speed doesn’t change it, only $C$ and $V$ do.⁵

Summed over all nodes, with $\alpha$ defined as the probability a node makes a 0→1 transition in a cycle, $P_{\mathrm{sw}} = \alpha C V_{\mathrm{DD}}^2 f$. Conventions differ: some texts count both edges and write $\tfrac{1}{2} \alpha C V^2 f$, so check which $\alpha$ a tool or paper reports. For a clock net $\alpha = 1$ under this definition. Completely random data gives $\alpha = 0.25$ (a node is 0 in one cycle and 1 in the next with probability $\tfrac{1}{2} \times \tfrac{1}{2}$), and typical logic sits near 0.1, because data passing through ANDs and ORs is biased toward one value.⁵ Glitches, spurious transitions before a node settles, push real activity back up.

The cubic lever

Switching power is quadratic in $V_{\mathrm{DD}}$ at fixed $f$. But $f_{\mathrm{max}}$ itself depends on $V_{\mathrm{DD}}$: from the alpha-power delay, $f_{\mathrm{max}} \propto (V_{\mathrm{DD}} - V_{\mathrm{T}})^{\alpha}/V_{\mathrm{DD}}$, which is roughly linear in $V_{\mathrm{DD}}$ over a typical DVFS range. Scaling $V$ and $f$ together therefore gives $P \propto V^3$ approximately, while energy per operation goes as $V^2$. That is the case for running wide and slow: Chandrakasan, Sheng and Brodersen showed in 1992 that you can lower the supply and recover the lost throughput with parallel or pipelined hardware, trading area for a large drop in power at the same throughput. Looking back on the paper, Chandrakasan describes this architectural voltage scaling as improving the power-delay product by an order of magnitude without losing performance.⁶

Example. Two copies of a datapath at half the clock deliver the same throughput as one at full clock. If halving $f$ lets $V_{\mathrm{DD}}$ fall from 1.0 V to 0.7 V, each copy burns $0.49 \times 0.5$ of the original, so the pair burns 0.49: half the power, for twice the area plus the cost of splitting and merging the data.

Short-circuit power

While the input slews through the window $V_{\mathrm{T,n}} < V_{\mathrm{in}} < V_{\mathrm{DD}} - |V_{\mathrm{T,p}}|$, both networks conduct and a crowbar current flows. Its energy scales with input transition time, so keeping input and output slews comparable keeps it small: under 10% of dynamic power by Harris’s estimate.⁵ If $V_{\mathrm{DD}} < V_{\mathrm{T,n}} + |V_{\mathrm{T,p}}|$ the window closes altogether, so short-circuit current vanishes at very low supply voltages.

Subthreshold conduction

Below threshold the channel is weakly inverted and current flows by diffusion, so it follows the Boltzmann distribution of carriers over the source barrier:

where $kT/q \approx 25.9\,\mathrm{mV}$ at 300 K and $n \ge 1$ is the ideality factor, set by how the gate capacitance divides with the depletion capacitance underneath it. For $V_{\mathrm{DS}}$ more than a few $kT/q$ the last factor is 1. Converting to base 10, current changes one decade per $S = n\,(kT/q) \ln 10$ millivolts: 59.5 mV/decade for $n = 1$ at 300 K, and 89 mV/decade for $n = 1.5$ (the value used in the simulation).⁴⁷

Setting $V_{\mathrm{GS}} = 0$ gives the off-current $I_{\mathrm{off}} \approx I_0 \cdot 10^{-V_{\mathrm{T}}/S}$. Three things make it worse in practice:

• DIBL. In short channels the drain field lowers the source barrier, so $V_{\mathrm{T}}$ falls with $V_{\mathrm{DS}}$ ($V_{\mathrm{T,eff}} = V_{\mathrm{T}} - \eta V_{\mathrm{DS}}$, with $\eta$ around 0.1 in Harris’s 65 nm example). Leakage then rises exponentially with $V_{\mathrm{DD}}$ as well, which is one reason lowering $V_{\mathrm{DD}}$ cuts leakage power by more than the linear $V_{\mathrm{DD}}$ factor suggests.⁴⁵
• Temperature. Heat lowers $V_{\mathrm{T}}$, and $kT/q$, and with it $S$, grows in proportion to absolute temperature ($S$ at 85 °C is 71 mV/decade even with $n = 1$). Off-current therefore rises with temperature while on-current falls, which is why leakage is estimated at the hot corner.⁴
• Stacking helps. Two off transistors in series leak about ten times less than one, because the node between them floats up and gives the upper device a negative $V_{\mathrm{GS}}$. Designers exploit this during sleep by choosing input values that turn off stacked devices.⁵

Gate and junction leakage

Gate leakage is carriers tunneling through the gate dielectric. It is exponentially sensitive to oxide thickness: negligible above about 2 nm, critically important at 65 nm and below, where the oxide is around 1 nm and gate leakage approaches subthreshold leakage.⁴⁵ $\mathrm{SiO_2}$ gate insulators stopped thinning at about 1.2 nm. High-k dielectrics with metal gates, first used in 45 nm microprocessors in 2007, restored a physically thicker barrier at the same capacitance and cut gate leakage by more than ten times.⁸ Junction leakage comes from the reverse-biased source and drain diodes, including band-to-band tunneling and gate-induced drain leakage at high doping levels.⁴

The on/off ratio

The useful figure of merit is $I_{\mathrm{on}}/I_{\mathrm{off}}$. With $V_{\mathrm{DD}} = 0.8\,\mathrm{V}$, $V_{\mathrm{T}} = 0.35\,\mathrm{V}$ and $S = 89\,\mathrm{mV/decade}$, the simulation’s device has $I_{\mathrm{on}}/I_{\mathrm{off}} \approx 1.4 \times 10^5$. Every 89 mV taken off $V_{\mathrm{T}}$ multiplies $I_{\mathrm{off}}$ by ten while raising $I_{\mathrm{on}}$ only modestly through the larger overdrive. Raising $V_{\mathrm{DD}}$ instead raises $I_{\mathrm{on}}$ but costs switching power as $V_{\mathrm{DD}}^2$. That is the trade the next section is about.

Choosing $V_{\mathrm{DD}}$ and $V_{\mathrm{T}}$ together

Fix a target delay. From the alpha-power model, delay $\propto V_{\mathrm{DD}}/(V_{\mathrm{DD}} - V_{\mathrm{T}})^{\alpha}$, so a family of $(V_{\mathrm{DD}}, V_{\mathrm{T}})$ pairs meets it, roughly a line of constant overdrive with a gentle tilt. Along that line, switching energy falls as $V_{\mathrm{DD}}^2$ while leakage rises as $10^{-V_{\mathrm{T}}/S}$. Total power has a minimum where the marginal saving in $\alpha C V_{\mathrm{DD}}^2 f$ equals the marginal cost in $V_{\mathrm{DD}} I_{\mathrm{off}}$.

Horowitz frames this as matching marginal costs. At the optimum, the energy spent per unit of delay saved must be the same whether it is bought with $V_{\mathrm{DD}}$ or with $V_{\mathrm{T}}$, and both equal the slope of the energy-performance Pareto curve. So neither voltage is set directly by scaling, and leakage was allowed to rise because that lowered total power.¹⁴ The National Research Council’s 2011 report puts the resulting balance at static leakage power of roughly 30% of dynamic power.⁹

The optimum depends on activity. A busy datapath (high $\alpha$) can afford more leakage per unit of switching and wants a lower $V_{\mathrm{T}}$; mostly idle logic and memory (low $\alpha$) leak for a long time per useful transition and want a higher one.¹⁴ There is no single best $V_{\mathrm{T}}$, which is why a process offers several.

Multi-$V_{\mathrm{T}}$ assignment

In SKY130 the low-$V_{\mathrm{T}}$ NMOS has the same cross-section as the standard device “except for the $V_{\mathrm{T}}$ adjust implants.” The kit exposes nfet_01v8_lvt, pfet_01v8_lvt and pfet_01v8_hvt alongside the standard nfet_01v8 and pfet_01v8, and its seven cell libraries are largely defined by which pair they use: hs pairs the two low-$V_{\mathrm{T}}$ devices, hd the two standard ones, and hdll and lp the standard NMOS with the high-$V_{\mathrm{T}}$ PMOS.¹⁰¹¹ ASAP7 provides SLVT, LVT, RVT and SRAM flavors, in decreasing order of drive strength, with off-current dropping by about an order of magnitude per step.¹²

Tools use the flavors in two directions. During timing repair they swap cells on failing paths to a faster flavor (OpenROAD’s repair_timing does this by default unless told to skip it). During power recovery they resize cells on paths with positive slack to save power, which with a multi-$V_{\mathrm{T}}$ library includes moving them to slower, lower-leakage flavors.¹³ The result is a design that is mostly high-$V_{\mathrm{T}}$ by cell count, with low-$V_{\mathrm{T}}$ concentrated on the critical paths; Harris’s worked example of a billion-transistor chip assumes high-$V_{\mathrm{T}}$ in all memories and 95% of logic gates.⁵ Because leakage is exponential in $V_{\mathrm{T}}$ and rises with temperature, leakage is checked at the hot, fast corner and timing at the slow corner (see PVT corners).

DVFS and power gating

DVFS moves along the delay-$V_{\mathrm{DD}}$ curve at run time. Each operating point needs its own timing signoff, a regulator that can slew between voltages, and a clock that can change frequency, so designs support a handful of points rather than a continuum. Lowering $V_{\mathrm{DD}}$ cuts leakage power more than linearly because of DIBL, but leakage energy per operation rises once each operation takes much longer: that tension produces the minimum energy point described in “Under the hood.” For long idle periods power gating removes the supply with a header or footer switch, eliminating leakage at the cost of state loss (or retention flip-flops) and wake-up time, and the switch’s own voltage drop slows the gated block while it runs.⁵

Dennard’s constant-field rules

Dennard, Gaensslen, Yu, Rideout, Bassous and LeBlanc scaled $t_{\mathrm{ox}}$, $L$ and $W$ by $1/\kappa$, the substrate doping by $\kappa$ and all voltages by $1/\kappa$, which keeps the electric-field pattern inside the device unchanged. Their Table I gives current per device $1/\kappa$, capacitance $1/\kappa$, delay $VC/I \propto 1/\kappa$, power per circuit $VI \propto 1/\kappa^2$, and power density constant.¹ Harris’s version of the same table adds switching energy per gate, $CV^2$, falling as $1/\kappa^3$.¹⁷

The paper flagged the exception itself: “one must accept the fact that the subthreshold behavior does not scale as desired.”¹ The subthreshold slope is $n\,(kT/q) \ln 10$, and $kT/q$ is a property of the operating temperature, not of the device size. For two decades that was harmless, because $V_{\mathrm{T}}$ was large compared with the slope. Historically $V_{\mathrm{T}}$ sat around 800 mV, and each generation that lowered it paid about a decade of off-current per 100 mV removed.⁹

What the data show

• Supply voltage. CPU DB, a database of decades of microprocessors, shows the knee: processors stayed at 5 V until about the 0.6 µm generation, then scaled roughly as the square root of feature size down to 0.13 µm, and scaling slowed from 0.13 µm on.¹⁵
• Power density. From the 80386 to 2005, feature size scaled about 16×, supply voltage about 4× and frequency about 200×, and processor power density rose more than 32×.¹⁵
• Frequency. In the processor trend data the fastest clock rises from about 200 MHz in 1993 to 3.65 GHz in 2004 and never passes 4.7 GHz afterwards.¹⁸

The ASAP7 authors summarize the cause from a device-kit perspective: Dennard scaling “has given way due to difficulty in reducing $V_{\mathrm{DD}}$ due to $I_{\mathrm{on}}/I_{\mathrm{off}}$ considerations, i.e., vanishing room for threshold voltage scaling while maintaining gate overdrive, and variability.”¹²

Scaling with fixed voltage

Scale dimensions by $1/\kappa$ with $V_{\mathrm{DD}}$ and $V_{\mathrm{T}}$ fixed. $C$ per gate still falls as $1/\kappa$ and density rises as $\kappa^2$, so switching power per area rises as $\kappa$ at constant frequency, and as $\kappa^2$ if you also take the frequency gain. Every later technique in this guide and the next is partly a response: FinFETs and gate-all-around devices improve gate control and therefore $n$ and the subthreshold slope (ASAP7’s modeled FinFETs sit at about 63 mV/decade, close to the 60 mV limit; see Shrinking), while multicore, DVFS, power gating and specialization spend transistors to save energy.¹²

Esmaeilzadeh et al. combined device projections with multicore performance models and estimated that 21% of a fixed-size chip would have to be powered off at 22 nm, rising to more than 50% at 8 nm.¹⁶ The exact percentages depend on their projections; the lasting point is that design became limited by power rather than by area. How architects spend a fixed power budget on cores, clock and vector width is worked through in Multicore and vector units.

The model: $I_{\mathrm{on}}$ follows the alpha-power law ($\alpha = 1.3$) above threshold and an exponential with $n = 1.5$ ($S \approx 89\,\mathrm{mV/decade}$) below it, joined smoothly. Gate delay is $K V_{\mathrm{DD}}/I_{\mathrm{on}}$, calibrated to 15 ps at 0.8 V and $V_{\mathrm{T}} = 0.35\,\mathrm{V}$, and $f_{\mathrm{max}} = 1/(30\, t_{\mathrm{pd}})$. Leakage is the same current model at $V_{\mathrm{GS}} = 0$, scaled with $C$. DIBL and temperature are left out. You also get $\alpha$ and $C$, and a second chart: energy per cycle when clocked at $f_{\mathrm{max}}$ for each $V_{\mathrm{DD}}$, decomposed into $\alpha C V^2$ and leakage energy. Find the minimum, then see how it moves when you change $\alpha$ (try 0.02) or $V_{\mathrm{T}}$, and try the “Near threshold” preset.

Threshold flavor and delay in SKY130

The SKY130 device documentation lists a 143-stage, fanout-of-one inverter chain for each device pairing at the typical corner. Changing only the threshold flavor moves the stage delay by roughly −10% to +20%:¹⁰

The process corners matter as much as the flavor: the standard pair spans 24.7 ps at the fast corner to 44.1 ps at the slow one.

A textbook leakage budget

Harris works through an example: a one-billion-transistor chip at 1.0 V with subthreshold leakage of 100 nA/µm for normal-$V_{\mathrm{T}}$ and 10 nA/µm for high-$V_{\mathrm{T}}$ devices, high-$V_{\mathrm{T}}$ in all memories and 95% of logic gates, and gate leakage of 5 nA/µm. The result is 584 mA of subthreshold and 275 mA of gate leakage: 859 mW of static power before a single gate switches. The same slides give typical 65 nm values of $I_{\mathrm{off}}$ = 100, 10 and 1 nA/µm at $V_{\mathrm{T}}$ = 0.3, 0.4 and 0.5 V, with $S = 100\,\mathrm{mV/decade}$ and a DIBL coefficient $\eta = 0.1$.⁵

Near threshold, measured

• Scaling from a nominal 1.1 V to 400–500 mV gives up to about 10× better energy efficiency, for roughly 10× lower performance. In an industrial 45 nm process the FO4 delay at 400 mV is 10× the delay at 1.1 V.¹⁹
• The minimum energy point is typically 250–350 mV, and it is shallow: going from near-threshold to subthreshold saves only about 2× more energy while delay rises 50–100×.¹⁹
• Calhoun, Wang and Chandrakasan measured the minimum at 250 mV for two filter circuits in 0.18 µm, with a ring oscillator slowing from 330 kHz at 300 mV to 29 kHz at 200 mV: an order of magnitude per 100 mV below threshold.²⁰

Energy, delay and the knee of the curve

Plot energy per operation against delay for every $(V_{\mathrm{DD}}, V_{\mathrm{T}}, \text{size})$ choice and the best designs form a convex Pareto front. At the fast end, a little more speed costs a lot of energy (high $V_{\mathrm{DD}}$, low $V_{\mathrm{T}}$, upsized gates). At the slow end, below the minimum energy point, you lose both. Practical designs sit near the knee, and DVFS lets them slide along it. Metrics such as energy-delay product ($E \cdot t$) pick a point near the knee; pure energy per operation picks the minimum energy point.

Variation near threshold

Above threshold, delay depends on $V_{\mathrm{T}}$ through $(V_{\mathrm{DD}} - V_{\mathrm{T}})^{-\alpha}$, a mild dependence. Near and below threshold the dependence of drive current on $V_{\mathrm{T}}$, $V_{\mathrm{DD}}$ and temperature approaches exponential. Dreslinski et al. report that performance variation from global process variation alone grows from about 1.3× at nominal voltage to about 5× at 400 mV, and that temperature and supply ripple can each add another 2×, for a total uncertainty near 20× against about 1.5× at nominal. Local mismatch from random dopant fluctuation and line-edge roughness also threatens circuits that hold state by positive feedback, SRAM above all. Near-threshold designs therefore need variation-tolerant clocking and architecture and special SRAM, which eats into the energy gain.¹⁹

Failure modes in signoff

• Corner selection. Setup is checked at slow process and low voltage, leakage at fast process and high temperature (see PVT corners). In SKY130 the same standard inverter is 24.7 ps per stage at the fast corner and 44.1 ps at the slow one, a spread larger than any threshold flavor change.¹⁰
• Activity assumptions. Dynamic power is only as good as $\alpha$. A default toggle rate can be far from what a real workload does, in either direction, so signoff power estimates use switching activity recorded from simulations of representative workloads.
• Dynamic IR drop. Simultaneous switching draws current spikes that sag the local supply. A gate whose $V_{\mathrm{DD}} - V_{\mathrm{T}}$ shrinks by a few tens of millivolts at 0.6 V loses far more speed than it would at 1.0 V, so low-voltage designs are more sensitive to supply noise.
• Mode transitions. DVFS changes must lower frequency before lowering voltage, and raise voltage before raising frequency; getting the order wrong gives a brief window where the clock is faster than the gates.

Fitting the alpha-power law

The alpha-power model replaces the square law’s two discrepancies with short-channel measurements: the saturation-region current no longer grows as the square of the overdrive, and the drain saturation voltage is shifted from the square-law value. Both come from velocity saturation. Its parameters, including $V_{\mathrm{T}}$ and $\alpha$, are fitted to measured I-V curves. With it, Sakurai and Newton derived closed-form expressions for inverter delay that include the input transition time. The simple $CV/I$ form used in this chapter is the step-input limit.³

Two cautions when you use it. First, it is an above-threshold model: it predicts zero current at $V_{\mathrm{GS}} = V_{\mathrm{T}}$, so anything near threshold needs a subthreshold term. The simulation joins the two with a soft-plus function, $I \propto \big[s \ln\big(1 + e^{(V - V_{\mathrm{T}})/s}\big)\big]^{\alpha}$ with $s = \alpha n\,kT/q$, which tends to $(V - V_{\mathrm{T}})^{\alpha}$ well above threshold and to an exponential with the right slope, one decade per $n\,(kT/q) \ln 10$, well below it. Second, $\alpha$ itself drifts with $V_{\mathrm{DD}}$, because velocity saturation weakens at low fields. Fits over a narrow DVFS range are good; extrapolation to near threshold is not.

The minimum energy point, derived

Clock a circuit at its maximum frequency for each $V_{\mathrm{DD}}$. One operation (one clock cycle) costs

where $L_{\mathrm{DP}}$ is the logic depth. This is the same decomposition Calhoun, Wang and Chandrakasan use for subthreshold circuits: switching energy plus $V_{\mathrm{DD}} I_{\mathrm{OFF}} T_{\mathrm{D}}$.²⁰

With $t_{\mathrm{pd}} = k C_{\mathrm{g}} V/I_{\mathrm{on}}(V)$ and the leakage of the whole block proportional to its size, the ratio of leakage to switching energy is

Each term in that ratio tells you something:

• $L_{\mathrm{DP}}/\alpha$: deep logic and low activity mean many idle gates leaking for a long cycle per useful transition. Leakage matters more, and the minimum moves to a higher voltage.
• $I_{\mathrm{off}}/I_{\mathrm{on}}(V)$: above threshold this changes slowly with $V$. Below threshold $I_{\mathrm{on}}(V)/I_{\mathrm{off}} \approx e^{V/(n\,kT/q)}$, so the leakage share grows exponentially as $V$ falls while $\alpha C V^2$ shrinks only quadratically. Their sum has a minimum.

In the subthreshold limit, write $x = V/(n\,kT/q)$ and $E = \alpha C V^2 (1 + A e^{-x})$, with $A$ collecting the constants above. Setting $dE/dV = 0$ gives $2(1 + A e^{-x}) = A x e^{-x}$, or $e^x = A(x - 2)/2$. The optimum depends on $A$ only logarithmically, which fits the observation that minimum energy points land in a narrow band, typically 250–350 mV, across very different circuits.¹⁹ Its position relative to $V_{\mathrm{T}}$ still shifts with activity and leakage.

The simulation’s numbers ($V_{\mathrm{T}} = 0.35\,\mathrm{V}$, 30-gate path) show the activity dependence directly:

These are properties of the toy model, not of any process. They do reproduce the qualitative findings of the near-threshold literature: savings of several times in energy per operation, paid for with roughly an order of magnitude in speed, and an optimum that sits near threshold.¹⁹

Assigning thresholds: a sensitivity-driven swap

Choosing a $V_{\mathrm{T}}$ flavor for each of millions of cells is a discrete optimization: minimize total leakage subject to every timing path meeting its constraint. Exact solutions are impractical at that scale, so implementation tools use incremental, sensitivity-driven heuristics that work alongside sizing and buffering. The general shape is:

1. Start from a low-leakage assignment (mostly HVT or RVT) and run static timing analysis.
2. For cells on violating paths, estimate each candidate swap’s benefit as delay gained per unit of leakage added, $\Delta t/\Delta P_{\mathrm{leak}}$, and apply the best ones.
3. Re-time incrementally, since a faster cell also changes the slew and load seen by its neighbors.
4. Run the reverse pass for power recovery: on paths with positive slack, swap cells to slower, lower-leakage flavors while the slack stays above a margin.

OpenROAD exposes both directions: $V_{\mathrm{T}}$ swapping during repair_timing (on by default) and a power-recovery option that works on a chosen percentage of paths.¹³ Because the swap preserves footprint and pins, it can run late, even after routing, which makes it one of the cheapest last-mile timing fixes available.