Memory cells

Memory cells are where device physics meets system architecture most directly. The cell’s storage mechanism fixes its area per bit, its access time, its energy per access and whether it needs power or refresh to keep its data, and those four numbers set the shape of the memory hierarchy above it.²

• 6T SRAM is a bistable latch built from logic transistors. It lives on the logic die, reads non-destructively and is fast, but six devices per bit make it the least dense. Its design problem is ratioed: the same access transistors must be weak enough not to disturb the cell on a read and strong enough to overpower it on a write.¹
• 1T1C DRAM stores charge on a dedicated capacitor. An SRAM cell takes roughly 20 times its silicon area per bit: about 120–140 $F^2$ against about 6 $F^2$, where $F$ is the process’s smallest feature.⁹ But a DRAM read is destructive, its signal is a small fraction of the supply after charge sharing, and it must be refreshed every 64 ms.¹¹
• NAND flash stores charge in a floating gate or charge trap isolated by oxide, shifting the cell’s threshold voltage. It keeps data unpowered and stores several bits per cell, at the cost of slow, high-voltage programming, block erase and limited endurance.¹⁴

The emphasis here is the circuit-level detail that decides whether a cell works at all: read stability, writability, the static noise margin and the butterfly curve for SRAM; the sensing budget and refresh for DRAM; and the charge-storage and wear mechanisms of flash. Numbers come from the open SKY130 process where possible.

The 6T cell is two cross-coupled CMOS inverters (pull-ups P1, P2; pull-downs N1, N2) plus two NMOS access transistors A1, A2 gated by the word line and connecting the storage nodes Q, QB to a differential bit-line pair. It is the cell in most commercial chips: cell area dominates array area, and six logic transistors give a compact cell that is static, differential and readable without destroying its data.¹

Read. Both bit lines are precharged and equalized to $V_{\mathrm{DD}}$, then the word line rises. On the side storing 0, the access transistor (saturated, $V_{\mathrm{GS}} = V_{\mathrm{DS}} = V_{\mathrm{DD}} - V_{\mathrm{Q}}$) and the pull-down (linear, $V_{\mathrm{GS}} = V_{\mathrm{DD}}$) form a ratioed divider, so Q rises from 0 to a read bump $V_{\mathrm{READ}}$ while the bit line discharges through the series pair. Bit-line delay goes as $t \propto (C/I)\,\Delta V$ with a large $C$ (every cell’s drain junction on the column) and a small $I$ (two minimum-size transistors in series), so arrays fire a clocked, latch-type sense amplifier as soon as the swing is large enough to resolve, and twist bit-line pairs so coupling noise lands on both lines equally.¹

Write. Write drivers pull one bit line to 0 and hold the other at $V_{\mathrm{DD}}$. The access transistor on the 0 side (linear, $V_{\mathrm{GS}} = V_{\mathrm{DD}}$) fights the pull-up holding that node at 1. If it wins by enough to pull the node below the opposite inverter’s trip point, positive feedback completes the flip; the other side helps a little, since its access transistor pulls the 0 node up from the $V_{\mathrm{DD}}$ bit line.⁴

Variants. Every access transistor added to the storage nodes adds another read disturbance, so multiported register files and low-voltage SRAMs isolate reads from the storage nodes with a separate read stack: an 8T cell (one read-only port) or a 10T cell. The price is area: the SKY130 dual-port 8T bitcell is 6.162 µm² against 1.896 µm² for the single-port 6T cell.¹¹⁵ A 10T sub-threshold design from MIT, whose separate read buffer removes the read disturbance, read correctly down to 320 mV.⁶

Read stability

During a read, the node storing 0 settles at $V_{\mathrm{READ}}$, set by the access/pull-down divider. The read is non-destructive if $V_{\mathrm{READ}}$ stays below the trip point $V_{\mathrm{TRIP}}$ of the inverter it drives, approximately that inverter’s switching threshold. Raising the cell ratio $\mathrm{CR} = W_{\mathrm{pd}}/W_{\mathrm{acc}}$ lowers $V_{\mathrm{READ}}$; commercial cells sit at $\mathrm{CR} \approx 1.5\text{–}2.5$. A minimum-size cell ($\mathrm{CR} = 1$, $\mathrm{PR} = 1$) is about 25% smaller than a $\mathrm{CR} = 2$ cell and has about 25% less read SNM; its read SNM can be restored with a 10% word-line underdrive during reads, which weakens the access transistor.⁴

Writability

With $\mathrm{PR} = W_{\mathrm{pu}}/W_{\mathrm{acc}}$, the access transistor must pull the 1 node below the opposite trip point against the pull-up. PR is usually 1 and must stay below a limit that guidelines put between about 1.8 and 3.⁴¹⁰ Write ability is quantified as a write margin: the write noise margin (the side of the smallest square spanning the two write-mode VTCs), the highest bit-line voltage that still writes, or the word-line voltage margin, which is easier to measure in an array.⁴¹⁰ On the butterfly, a successful write is a plot with a single crossing (a “negative SNM”); a failed write still has two lobes.⁶

SNM and the butterfly

Seevinck, List and Lohstroh defined the static noise margin in 1987 as the side of the largest square nested between the two VTCs, equivalent to the largest DC noise voltage that can be inserted in series with both inverter inputs (in the adverse direction) before the loop loses bistability.⁶ Read SNM is measured by holding the word line and both bit lines at $V_{\mathrm{DD}}$, breaking the loop and sweeping each half-cell.⁵ The measures are not interchangeable:

• Hold SNM (WL = 0) is bounded by $V_{\mathrm{DD}}/2$, even for ideal inverters.¹⁰
• Read SNM (WL = 1, BL = BLB = $V_{\mathrm{DD}}$) is the worst case in a 6T cell and rises with CR.⁶¹⁰
• Write margin is not read off the hold or read butterfly; it needs the asymmetric write configuration.¹⁰⁵

SNM is a DC metric. It ignores how long a disturbance lasts: a short enough noise pulse can exceed the SNM without flipping the cell, and dynamic noise-margin criteria, which depend on pulse width and the cell’s own response time, capture that.⁷

Variation sets Vmin

Random dopant fluctuation gives each transistor a threshold offset whose spread grows as channel area shrinks.⁴ Mismatch between N1 and N2 (or between the access devices) skews the butterfly: one lobe grows, the other shrinks, and the cell’s SNM is the smaller lobe. An array needs every cell to have positive margin, so the SNM distribution is evaluated far into its tail, out to $6\sigma$.⁶ That is why SRAM often sets a chip’s minimum operating voltage: in 2006, 65 nm 6T memories usually ran at 0.9 V or more (the lowest reported was 0.7 V), while a 10T cell that removes the read disturbance read at 320 mV and wrote at 380 mV at room temperature.⁶

Activation. All bit lines in a bank are precharged to $V_{\mathrm{DD}}/2$. ACTIVATE raises one word line and the selected row’s cells share charge with their bit lines, moving each by $\Delta V = (V_{\mathrm{cell}} - V_{\mathrm{DD}}/2)\,C_{\mathrm{S}}/(C_{\mathrm{S}} + C_{\mathrm{BL}})$. With a charge transfer ratio of 1–10%, the signal is only a few percent of the cell’s voltage swing.¹⁰ The sense amplifiers (cross-coupled latches on each bit line, collectively the row buffer) then regenerate the bit line to the rail.¹⁷¹¹ The bit line reaches a usable level ($0.75\,V_{\mathrm{DD}}$ or $0.25\,V_{\mathrm{DD}}$) after tRCD, when READ or WRITE may be issued, and the cell is fully restored after tRAS; PRECHARGE then returns the bit lines to $V_{\mathrm{DD}}/2$ in tRP.¹²

Bit-line capacitance is the latency. A long bit line lowers $\Delta V$ and slows both amplification and precharge, because the sense amplifier must move $C_{\mathrm{S}} + C_{\mathrm{BL}}$ at a fixed drive. But each bit line needs its own sense amplifier, so short bit lines multiply sense-amplifier area. In transistor-level simulations based on a 55 nm DDR3 process, cutting a bit line from 512 to 32 cells reduced tRCD from 15 ns to 8.2 ns and tRC from 52.5 ns to 23.1 ns, but grew the die 3.76×. Commodity DRAM chooses long bit lines and cheap bits.¹²

Refresh. Charge leaks only off the storage node (a stored 0 can’t gain charge), so retention errors are 1→0. The 64 ms interval is set by the leakiest cells; most cells retain data far longer. The controller issues auto-refresh every $\mathrm{tREFI} = 7.8\,\mu\mathrm{s}$ (3.9 µs above 85 °C), and each command blocks the rank for tRFC, on the order of 300 ns, closing all open rows.¹¹ That works out to $64\,\mathrm{ms} / 7.8\,\mu\mathrm{s} \approx 8{,}200$ refresh commands per interval and roughly $\mathrm{tRFC}/\mathrm{tREFI} \approx 4\%$ of the rank’s time at normal temperature. Because tRFC grows roughly linearly with chip density, refresh was projected to cost nearly 50% of throughput at 64 Gb densities in the extended temperature range, without changes such as retention-aware refresh.¹¹

Disturbance. Dense cells couple. Repeatedly activating one row between refreshes accelerates leakage in neighbors (RowHammer): a 2014 study induced errors in 110 of 129 modules from three manufacturers, with as few as 139K activations, and found up to one cell in 1.7K susceptible.¹³

Mechanism. Program and erase move charge through the tunnel oxide by Fowler–Nordheim tunneling, $J_{\mathrm{FN}} = \alpha E_{\mathrm{ox}}^2 \exp(-\beta/E_{\mathrm{ox}})$, which is exponential in the oxide field. Programming uses incremental step-pulse programming (ISPP): high-voltage pulses on the selected word line, each followed by a verify, until the cell crosses its target threshold. ISPP can only add charge, so data changes require a block erase (the substrate is raised to $V_{\mathrm{erase}}$ with the control gates grounded).¹⁴

Levels and errors. SLC uses two threshold states, MLC four, TLC eight, each assigned a window within the same overall range, so each extra bit halves the window per state. Programmed thresholds drift: stress-induced leakage through the tunnel oxide slowly moves charge off the gate after programming (retention errors), reads disturb unselected cells on the same string, and neighbors couple during programming.¹⁴

Endurance. Each program/erase (P/E) cycle damages the oxide. 50–59 nm MLC endured about 10,000 P/E cycles per block; 15–19 nm MLC and TLC about 3,000 and 1,000. 3D NAND reversed the trend for a while: with 48–64 stacked layers it could use larger features (about 50–54 nm), and its charge-trap cells are less prone to oxide breakdown, raising endurance by over an order of magnitude, though charge-trap cells leak faster soon after programming, including sideways along the vertical channel.¹⁴

The model is a long-channel square-law 6T cell ($V_{\mathrm{DD}} = 1\,\mathrm{V}$, $|V_{\mathrm{T}}| = 0.3\,\mathrm{V}$, PMOS at half the NMOS strength per width); curves are solved by bisection and the SNM found with the 45° rotation method described in Under the hood. Mismatch adds $+\Delta V_{\mathrm{T}}$ to N1 and $-\Delta V_{\mathrm{T}}$ to N2, so the Q = 0 lobe is the weak one. With $\Delta V_{\mathrm{T}}$ at 0, check that read SNM at $\mathrm{CR} = 1$ is roughly a quarter below $\mathrm{CR} = 2$; find the PR at which the write margin closes; and see how much $\Delta V_{\mathrm{T}}$ a $\mathrm{CR} = 1$ cell tolerates before a read upsets it. The lower panel models DRAM sensing: choose $C_{\mathrm{BL}}/C_{\mathrm{S}}$ and the time since refresh, and see when a decayed 1 falls below an illustrative ±30 mV sense threshold.

Array efficiency in an open process. OpenRAM’s second SKY130 test chip (MPW2) lists its macros’ outlines.¹⁵ Multiplying bits by the 1.896 µm² bitcell shows how much of each macro is actually storage:

Decoders, sense amplifiers, write drivers, control and power rings are a fixed overhead, so small macros are mostly periphery and density per bit improves with macro size. Measurements of the project’s first test chip, a 1 KB dual-port (8T) macro, show how much voltage headroom an SRAM array has in hold: written at 1.8 V, the first retention errors appeared at 440 mV cold and 410 mV hot.¹⁵

Margins and timing. Read SNM falls about 25% when CR goes from 2 to 1.⁴ In DRAM, the activate-to-read delay tRCD is 15 ns and the row cycle tRC 52.5 ns for a 512-cell bit line, against 8.2 ns and 23.1 ns for 32 cells at 3.76× the die area; over an 11-year span DRAM cost per bit fell 16× while tRCD and tRC improved by only about 30% and 26%.¹²

Energy. In a spatial accelerator, normalized energy per access is about 1× for a 0.5–1 kB register file, 2× for a neighboring processing element, 6× for a 100–500 kB global SRAM buffer and 200× for DRAM.¹⁶

Where each technology sits

The hierarchy follows directly: an L1 is limited by the largest SRAM that keeps hit time at 1–2 cycles,³ DRAM supplies capacity at a latency (tens of nanoseconds per activate) that barely improved over the 11 years one study examined, because manufacturers spend scaling on cost per bit,¹² and flash supplies persistence. For accelerators, the energy ratio matters as much as the latency: with DRAM accesses about 200× a register-file access, dataflow is chosen to maximize on-chip reuse, and on-chip SRAM capacity becomes a first-order architectural parameter.¹⁶ The Architectures chapter The memory wall quantifies this for inference, including HBM, the stacked DRAM placed in the package (see Packaging and chiplets).

Failure modes and what designers do about them

• SRAM $V_{\mathrm{min}}$. Read SNM collapses first as $V_{\mathrm{DD}}$ drops and mismatch grows; write failures appear at fast-PMOS/slow-NMOS corners. Remedies: upsized or 8T/10T cells for low-voltage or multiport arrays, read/write assists, a separate boosted word-line supply, and row/column redundancy that replaces failing cells after test.⁶⁴
• DRAM refresh overhead and retention tails. Retention is log-normally distributed with a tail of leaky cells; refreshing everything at the leakiest cell’s rate wastes energy and bandwidth that grow with density, which motivates retention-aware refresh.¹¹
• DRAM disturbance. RowHammer showed that inter-cell coupling at small pitch is a correctness and security issue, not only a reliability one.¹³
• Flash retention, disturb and wear, handled in the controller with ECC, read-retry and wear leveling.¹⁴

1. The read bump from the square law

Use the long-channel model from The I-V curve: $I = \tfrac{\beta}{2}(V_{\mathrm{GS}} - V_{\mathrm{T}})^2$ in saturation and $I = \beta\left[(V_{\mathrm{GS}} - V_{\mathrm{T}})V_{\mathrm{DS}} - \tfrac{1}{2}V_{\mathrm{DS}}^2\right]$ in the linear region, with $\beta$ proportional to $W/L$. During a read with Q = 0 and QB = $V_{\mathrm{DD}}$:

• The access transistor has its gate at $V_{\mathrm{DD}}$, drain on the bit line at $V_{\mathrm{DD}}$ and source at $Q = V$. $V_{\mathrm{DS}} = V_{\mathrm{GS}}$, so it is saturated: $I_{\mathrm{acc}} = \tfrac{\beta_{\mathrm{acc}}}{2}(V_{\mathrm{DD}} - V - V_{\mathrm{T}})^2$.
• The pull-down has $V_{\mathrm{GS}} = V_{\mathrm{DD}}$ and a small $V_{\mathrm{DS}} = V$, so it is linear: $I_{\mathrm{pd}} = \beta_{\mathrm{pd}}\left[(V_{\mathrm{DD}} - V_{\mathrm{T}})V - \tfrac{1}{2}V^2\right]$.

Setting the two equal with $\mathrm{CR} = \beta_{\mathrm{pd}}/\beta_{\mathrm{acc}}$ gives a quadratic in $V$:

Its smaller root has a tidy closed form:

With $V_{\mathrm{DD}} = 1\,\mathrm{V}$ and $V_{\mathrm{T}} = 0.3\,\mathrm{V}$: $\mathrm{CR} = 1$ gives 0.205 V, $\mathrm{CR} = 1.5$ gives 0.158 V and $\mathrm{CR} = 2$ gives 0.128 V. The bump shrinks with CR, but slowly: doubling CR from 1 to 2 removes only about a third of it. The read is safe while $V_{\mathrm{READ}}$ stays below the trip point of the inverter driven by Q, which is itself raised slightly by its own access transistor pulling QB up. This is the calculation behind the rule “pull-down much stronger than access”.¹⁴

2. The write condition

Writing Q from 1 to 0: BL = 0, QB = 0, so the pull-up P1 has its full $V_{\mathrm{SG}} = V_{\mathrm{DD}}$. The access transistor (source on BL at 0 V, $V_{\mathrm{GS}} = V_{\mathrm{DD}}$) is linear; the pull-up is saturated while $V_{\mathrm{Q}}$ is below $|V_{\mathrm{T}}|$:

which gives

as long as the result is below $V_{\mathrm{T}}$ (beyond that the pull-up leaves saturation and $V_{\mathrm{Q}}$ must be solved numerically). With $\mu_{\mathrm{p}}/\mu_{\mathrm{n}} = 0.5$ and $\mathrm{PR} = 1$, $V_{\mathrm{Q}} \approx 0.205\,\mathrm{V}$, well below the opposite inverter’s trip point (about 0.5 V here, raised slightly because its own access transistor is pulling QB up from BLB), so the write succeeds. Raising PR raises $V_{\mathrm{Q}}$; once it crosses the trip point the write fails. In this model that happens near $\mathrm{PR} \approx 2$, consistent with the guideline of keeping PR below about 1.8.¹⁰ The write noise margin generalizes this to the full VTCs.⁴

3. Computing SNM: the 45° rotation

Finding the largest square between two curves by brute force is awkward. Because both VTCs are monotonically decreasing, the largest square in a lobe has two opposite corners on the two curves and its diagonal along the direction $(1, 1)$. Rotate coordinates by 45°:

In the rotated frame each curve is a single-valued function $v(u)$, and the gap $v_1(u) - v_2(u)$ at a given $u$ is the diagonal of a square that fits between the curves at that position. So

taken separately for $u < 0$ and $u > 0$, and the cell’s SNM is the smaller of the two.⁷ If, in one lobe, the gap never has the expected sign, the curves cross only once on that side: the cell is monostable in that state and the margin is zero (or negative, if you keep the sign). The simulation above uses exactly this procedure on 90-point curves.

Assumptions to keep in mind: the method is static (DC), it treats the two halves as independent once the loop is cut, and it measures the margin to a noise source applied in the most damaging direction on both nodes at once. Dynamic criteria, which include the noise pulse width and the cell’s internal time constants, are needed when pulses are short.⁷

4. Designing for the tail

For an array of $N$ cells with independent margins, the probability that every cell works is $(1 - p)^N \approx \exp(-Np)$, where $p$ is the probability one cell fails. Keeping a 1 MB array ($N \approx 8.4 \times 10^6$) failure-free with, say, 99% probability needs $p \approx 1.2 \times 10^{-9}$, about $6\sigma$ for a Gaussian margin. Because local $V_{\mathrm{T}}$ mismatch has a standard deviation that grows as channel area shrinks,⁴ and analytic models are used to estimate the SNM distribution’s tail (plain Monte Carlo would need billions of samples to see a $10^{-9}$ event),⁶ $V_{\mathrm{min}}$ is set by the worst cells, and redundancy (spare rows and columns mapped in after test) relaxes the requirement on $p$.

5. DRAM sensing budget

Charge conservation at the moment the access transistor turns on:

so $\Delta V = V_{\mathrm{final}} - V_{\mathrm{pre}} = (V_{\mathrm{cell}} - V_{\mathrm{pre}})\,C_{\mathrm{S}}/(C_{\mathrm{S}} + C_{\mathrm{BL}})$.¹⁰ With $V_{\mathrm{pre}} = V_{\mathrm{DD}}/2$ the signals for a stored 1 and 0 are symmetric only when the 1 is fresh. A stored 1 leaks toward 0 between refreshes, so its signal shrinks first; a 0 cannot gain charge.¹¹ The sense amplifier needs $\Delta V$ larger than its input offset (set by mismatch between its own transistors) plus coupling noise from neighboring bit lines. That gives the design equation the simulation plots: for a given ratio $r = C_{\mathrm{BL}}/C_{\mathrm{S}}$ and minimum signal $\Delta V_{\mathrm{min}}$, a 1 is still read correctly while

and the refresh interval must be shorter than the time the leakiest cell takes to fall to that level. Longer bit lines (larger $r$) raise the required cell voltage and shorten the allowed interval, which is the density-versus-retention trade in one line.¹²

6. Refresh arithmetic

Refresh overhead $\approx \mathrm{tRFC}/\mathrm{tREFI}$. With $\mathrm{tREFI} = 7.8\,\mu\mathrm{s}$ and $\mathrm{tRFC} \approx 300\,\mathrm{ns}$, about 3.8% of the rank’s time is spent refreshing; at extended temperature ($\mathrm{tREFI} = 3.9\,\mu\mathrm{s}$) it doubles. Since tRFC scales roughly with the number of rows refreshed per command, and therefore with density, the overhead grows with every generation. RAIDR’s observation is that only a tiny fraction of cells need 64 ms: in a 32 GB system only about 30 cells could not tolerate a 128 ms interval and about 1,000 could not tolerate 256 ms, so binning rows by retention time lets most rows be refreshed far less often.¹¹

7. Flash programming

Fowler–Nordheim current density $J_{\mathrm{FN}} = \alpha E_{\mathrm{ox}}^2 \exp(-\beta/E_{\mathrm{ox}})$ rises exponentially with the oxide field, which is why programming uses pulses of high voltage and why a slightly weakened oxide leaks measurably over months. ISPP raises the program voltage by a fixed step per pulse and verifies after each one, so the final threshold distribution width is set by the step size: smaller steps give tighter distributions (needed for TLC and QLC) at the cost of more pulses and slower programming.¹⁴