Fins and nanosheets

Planar bulk, FinFET and lateral GAA are all versions of one device, the insulated-gate field-effect transistor, told apart by the number of gated faces: one (planar), two or three for the multigate double-gate and tri-gate FinFETs, and four (nanowires and nanosheets). Stacked variants such as the forksheet and the CFET rearrange nanosheets within a cell rather than adding gated faces.¹⁵

The electrostatic argument (natural length versus gate length) is in Shrinking. Here the figures of merit are per device and per footprint: effective width per unit of layout width, gate capacitance including parasitics, SS and DIBL as they feed into the supply voltage, variability, thermal resistance, and the process modules each step added. The brand names (Tri-Gate, RibbonFET, MBCFET) are implementations of these generic types, not further types.

Per device, the gated perimeter is

and to first order both drive current and intrinsic gate capacitance scale with it. The quantity that moved with each architecture is $W_{\mathrm{eff}}$ per unit of layout width. A FinFET’s footprint is set by the fin pitch, and its fin width is pinned by electrostatics (Berkeley’s data tie DIBL to $W_{\mathrm{fin}}$),¹¹ so the only free knob is fin height, which is a single process-wide value traded between layout efficiency and design flexibility.¹¹ ASAP7 gives $2 \times 32 + 6.5 = 70.5\,\mathrm{nm}$ per 27 nm of pitch, with at most three fins per device in its 7.5-track cell.¹²

A nanosheet decouples the two jobs. The thin dimension $t$, set by epitaxial growth, carries the electrostatics; width $w$ and sheet count $n_{\mathrm{sh}}$ add perimeter. That is also why industry chose sheets over nanowires: a wire is as good electrostatically, but it carries little current and each extra wire adds capacitance.⁸ Samsung’s 2022 release makes the same contrast, “nanosheets with wider channels” against nanowires with narrower ones.⁴ Intel described RibbonFET as reaching “the same drive current as multiple fins in a smaller footprint.”²

The limits move rather than vanish. Sheet width trades directly against cell height: imec notes that designers can widen the channels, “trading cell height for larger drive current.”¹⁵ Each added sheet brings another gap that gate metal fills right next to the source and drain, and with it more parasitic capacitance, which inner spacers exist to limit.⁸¹³ And as cells shrink, sheets get narrower, which lowers drive and raises the parasitic share again.¹⁶

A simple way to see the supply-voltage payoff: with a fixed off-current budget of $D$ decades below the threshold current, the threshold at full drain bias must be at least $\mathrm{SS} \cdot D$, and DIBL lowers it by $\mathrm{DIBL} \cdot V_{\mathrm{DD}}$. Holding a fixed overdrive $V_{\mathrm{ov}} = V_{\mathrm{DD}} - V_{\mathrm{T}}$ for the on-current gives

With $D = 4$ and $V_{\mathrm{ov}} = 0.45\,\mathrm{V}$, an illustrative short planar device (90 mV/dec, 100 mV/V) needs 0.90 V; a FinFET at 65 mV/dec and 25 mV/V (close to ASAP7’s 63.0 and 21.3) needs 0.73 V; a nanosheet at 62 mV/dec and 15 mV/V needs 0.71 V. At $E \propto C V_{\mathrm{DD}}^2$ the first step is worth about 35% of switching energy at equal capacitance; the second is small, because the FinFET was already near the 60 mV/dec floor. The nanosheet’s case rests more on drive per footprint and on holding these numbers at a shorter gate. The numbers are illustrative; the shape of the argument is that suppressing $I_{\mathrm{off}}$ “allows for reductions in $V_{\mathrm{TH}}$ and hence $V_{\mathrm{DD}}$.”¹¹¹²

Thin undoped bodies remove random dopant fluctuation and the mobility loss of heavy channel doping. What remains: $V_{\mathrm{T}}$ must be set by gate work function (or effective length), performance is very sensitive to fin width, and work-function variation dominates in undoped channels; below about 10 nm gate length, source/drain dopants diffusing into the channel bring a new performance-variability trade.¹¹ In a nanosheet the thin, electrostatics-setting dimension comes from epitaxial layer growth rather than from etching a fin,¹³ so the fin-width term becomes a sheet-thickness term.

In a bulk FinFET the fin is etched, the STI fill is recessed to set the fin reveal, and a punch-through stopper (super-steep retrograde well) is placed at the fin base under the gated region.¹¹ Fin width comes from lithography and etch, which is why performance is so sensitive to it.¹¹

The GAA-specific modules, as one open study lays them out:¹³

• Superlattice epitaxy. Si/SiGe layers with about 30% Ge and about 9 nm per layer in that work; sheet thickness and spacing are set by growth.
• Inner spacer. A lateral cavity etch of the SiGe ends, dielectric deposition and an etch-back. The spacer cuts gate-to-S/D capacitance and protects the S/D epitaxy during release. Depth is a trade: too shallow leaves capacitance (hurting AC performance), too deep adds extension resistance and short-channel effects, and the optimum is put at under about 5 nm. The cavity etch must be isotropic and stop on a flat front, so etch rate control matters more than selectivity here.
• Channel release. Here selectivity is everything: all the SiGe must go with almost no Si loss. Hot HCl gas etching runs at 600–760 °C, an unwelcome thermal budget; plasma (RIE) etching damages the sheet surfaces; wet etching risks sheets collapsing by capillary forces. The study used a remote-plasma, cyclic oxidize-and-etch process at room temperature and released sheets 30 to 80 nm wide.

Release is followed by the replacement metal gate: the gate dielectric and metals are deposited by atomic layer deposition so that they coat every sheet, including the faces that look at each other across a gap of a few nanometers.⁸

The generic vocabulary is older than the brands. “Tri-gate” and “double-gate” describe how many fin faces are gated, and Berkeley’s course material uses both as device types.¹¹ Intel’s 2011 “Tri-Gate” was a tri-gate FinFET with 8 nm fins and 26 nm gates.¹⁰ For GAA, “nanowire” and “nanosheet” distinguish channel aspect ratio; MBCFET (Samsung, marked with a trademark symbol in its release), RibbonFET (in IEEE Spectrum’s words, “Intel’s take on nanosheet, or gate-all-around, transistors”) and TSMC’s plain “nanosheet” are all gate-all-around transistors with sheet-shaped channels.⁴⁹⁶

What differs between implementations is published only in part: sheet count, width options, thickness, gate stack and what is built around the device. Each company has highlighted something different. Samsung stressed adjustable sheet width for design-technology co-optimization;⁴ TSMC’s NanoFlex puts cells with different sheet widths on one chip;⁶ Intel pairs RibbonFET with PowerVia, its backside power delivery.³ None of these changes the device category. When reading a comparison, map each name to the generic type first, then compare the published numbers, which are usually whole-process claims rather than transistor measurements.

imec’s roadmap gives GAA nanosheets at least three generations. The inner-wall forksheet places an 8–10 nm dielectric wall mid-cell before gate patterning; the sheets become tri-gate forks on each side of it, which reduces n-p spacing (17 nm at VLSI 2021) and parasitic capacitance between the two devices. Its manufacturability concerns are the thin wall surviving every later front-end etch, n/p masks that must land on it, the wall blocking the common n-p gate that imec says 90% of devices in real designs share, and the loss of the fourth gated face.¹⁵

The outer-wall forksheet (VLSI 2025, TCAD) moves the wall to the cell boundary as a p-p or n-n wall of about 15 nm, shared with the neighboring cell, and builds it wall-last, after channel release and S/D epitaxy. imec reports both forksheets reach 90 nm cell height at A10 against 115 nm for an A14 nanosheet.¹⁵ After that, imec places the monolithic CFET at A7.¹⁶

A geometry-only model: the same current and intrinsic capacitance per micron of gated width for every shape (calibrated to ASAP7’s RVT nFET, 37.9 µA per 70.5 nm fin), plus illustrative parasitics: gate fringing that scales with footprint and an inner-spacer term per sheet. It isolates what the architecture changes in layout, quantization and capacitance; electrostatics are in the Shrinking sim. The model and live values are shown below the plot.

The self-heating study modeled a 7 nm SOI FinFET and a 5 nm lateral stacked-nanowire GAAFET on a buried oxide, solving the 3D heat equation per device and superposing it over cells. Heat in the GAA case leaves mostly through the interconnect. Beyond temperature it reports delay degradation from BTI and HCI up to 25% (FinFET) and 39% (GAAFET), and electromigration lifetime of wires down by up to 38% and 45%.¹⁴

• Electrostatics vs parasitics. Fringing capacitance between the gate and the top and bottom of the S/D, and parasitic resistance (uniform S/D doping is hard to get by implantation in a fin), are listed among the remaining FinFET challenges.¹¹ In GAA, each sheet adds gate-to-S/D capacitance through its inner spacer, and as cells shrink, narrower sheets lower drive while parasitics rise, which is why imec’s CFET work lists parasitic-capacitance reduction among its performance boosters.¹³¹⁶
• Thermal resistance. In the Minnesota study’s models, average gate self-heating rose from 12 K (7 nm SOI FinFET) to 17 K (5 nm GAAFET), with BTI/HCI delay degradation up to 25% and 39% and electromigration lifetime reductions up to 38% and 45%.¹⁴
• Variability moves. Undoped channels remove random dopant fluctuation, but fin-width sensitivity and work-function variation take its place.¹¹
• Inner-spacer depth. Shallow keeps capacitance; deep adds resistance and short-channel effects.¹³
• Forksheet’s bargain. Tighter n-p spacing and lower n-p capacitance, paid for with a tri-gate fork instead of full GAA and a harder process; the outer-wall version aims to keep the density with fewer of those costs.¹⁵

The footprint model in the sim

The sim compares shapes by layout alone. It gives every shape the same current and intrinsic gate capacitance per unit of gated width, so any difference comes from geometry. The drive density is calibrated to ASAP7’s RVT nFET (37.9 µA per fin of 70.5 nm effective width at 0.7 V).¹² The parasitic terms are illustrative stand-ins for the two effects the sources name: fringing between the gate and the source/drain, which grows with the device’s footprint, and the extra gate-to-S/D coupling of each added sheet.¹¹⁸¹³

J      = 37.9 uA / 70.5 nm             drive per nm of gated width
Weff   = W                             planar
       = n (2H + 6.5)                  FinFET, fin 6.5 nm thick
       = k * 2 (w + 5)                 nanosheet, sheets 5 nm thick
foot   = W + 20.5                      planar: width + isolation gap
       = n * 27                        FinFET: n fin pitches
       = w + 20.5                      nanosheet: width + gap
I      = J * Weff
C_int  = 0.8 aF/nm * Weff              gate oxide over the channel
C_par  = 0.3 aF/nm * foot              fringing to source/drain
       + 0.2 aF/nm * w * k             inner-spacer coupling (sheets)
speed  = I / (C_int + C_par)           relative to 2 fins, H = 32 nm

Two results fall out. First, $W_{\mathrm{eff}}$ per footprint: about 2.6 for a 32 nm fin (70.5 over 27 nm) and about 4.2 for three 30 nm sheets (210 over 50.5 nm), against under 1 for planar. Second, because $C_{\mathrm{int}}$ and $I$ both scale with $W_{\mathrm{eff}}$, the ratio $I/C$ depends only on how large the parasitics are relative to the channel: taller fins and wider sheets raise it, while adding a sheet adds both channel and inner-spacer coupling.

Quantization, stated precisely

With fin height $H$ fixed by the process, a FinFET’s reachable drive is the set $\{ n J (2H + W_{\mathrm{fin}}) : n = 1 \dots n_{\max} \}$, with $n_{\max} = 3$ in ASAP7’s cell.¹² A nanosheet stack of $k$ sheets reaches the interval $[2kJ(w_{\min} + t),\; 2kJ(w_{\max} + t)]$, and the union over $k$ overlaps, so any target in range is reachable to within the layout grid. The sim’s Match button solves exactly this: the nearest fin count, or the sheet width for the current $k$.

What it leaves out

• Electrostatics: SS, DIBL and leakage are the same for all shapes here. The Shrinking chapter’s sim models them.
• Mobility differences between surfaces (fin sidewalls and sheet faces lie on different crystal planes), and strain.
• Series resistance of narrow fins and sheets, and the current crowding near the bottom sheet.
• Self-heating, which grows with power density and is worse for oxide-wrapped channels.

Production kits fold all of this into a compact model per device type; ASAP7 uses BSIM-CMG for its FinFETs.¹²