Shrinking

This chapter is about the electrostatic limit of MOSFET scaling and the architectural moves that pushed it back. The central quantity is the natural length $\lambda$, the distance over which source and drain potentials decay into the channel. When the gate length $L$ is many $\lambda$ long, the gate alone sets the barrier; when $L$ approaches a few $\lambda$, the drain shares control, which shows up as DIBL, a degraded subthreshold swing, threshold roll-off and finally punch-through.⁵

$\lambda$ shrinks with a thinner channel, a thinner EOT and more gated sides. Planar bulk devices ran out of the first two; SOI and then the FinFET attacked channel thickness and gate count, and gate-all-around nanosheets take both to their practical limit. Beyond that, density comes from stacking (CFET), from the wiring (backside power) and from DTCO, not from a shorter gate. FinFET-era numbers here come from ASAP7, an open, predictive 7 nm process design kit from Arizona State University and Arm Research.⁷

Dennard’s constant-field rules (Table I of the 1974 paper) scale dimensions, $V$ and $I$ by $1/\kappa$ and doping by $\kappa$: delay per circuit $1/\kappa$, power per circuit $1/\kappa^2$, power density 1.² Two caveats in the same paper defined the next forty years. First, the subthreshold slope is $(kT/q) \ln 10 \cdot m$ and doesn’t scale with dimensions, so $V_{\mathrm{T}}$ and $V_{\mathrm{DD}}$ can’t follow $1/\kappa$ without an exponential $I_{\mathrm{off}}$ penalty. Second, the source and drain depletion regions must not merge under the gate, or threshold control is lost and the device punches through; the paper’s shallow junctions and surface implant were there to prevent that.²

The first caveat ended constant-field scaling around 2005. The ASAP7 authors summarize the post-Dennard regime: $V_{\mathrm{DD}}$ stalled because of $I_{\mathrm{on}}/I_{\mathrm{off}}$ constraints and variability, gains came from strain and high-k/metal gates, FinFETs relieved short-channel effects and allowed a little more $V_{\mathrm{DD}}$ scaling, and ASAP7 assumes only about 100 mV or less of $V_{\mathrm{DD}}$ reduction from 14 nm to 7 nm, with drive current up about 15% per node.⁶ After about 2005, progress was “equivalent scaling” (HKMG, FinFETs, strain) rather than purely geometric.⁵

The second caveat is the subject of the rest of this chapter. Gate length is the one dimension electrostatics won’t let you shrink freely, which is why it stopped tracking pitch (it shrank faster than pitch from the mid-1990s, then slower) and why node names drifted away from it.⁴¹⁴

In the off state the drain current is diffusion over the source-channel barrier, $I \propto \exp(-E_{\mathrm{b}}/kT)$. A long-channel gate moves $E_{\mathrm{b}}$ by $\Delta V_{\mathrm{G}}/m$, where $m = 1 + C_{\mathrm{dep}}/C_{\mathrm{ox}}$ is the body factor, so

with $m$ about 1.2–1.5 in conventional bulk devices.³ A fully depleted thin body with no depletion charge to speak of pushes $m$ toward 1, which is the first gift of SOI and multigate devices.

Short channels add a second loss. The channel potential obeys a 2D Poisson equation; reduced to one dimension along the channel, the deviation from the long-channel potential decays from each junction as $\exp(-y/\lambda)$. The barrier peak sits where the two tails meet, so both its height and the gate’s leverage on it fall as the tails overlap:

• Roll-off and DIBL. The peak is lowered by roughly $2\sqrt{E_{\mathrm{b}}(E_{\mathrm{b}} + qV_{\mathrm{DS}})}\, e^{-L/2\lambda}$. Its $V_{\mathrm{DS}}$ dependence is DIBL; its $L$ dependence is $V_{\mathrm{T}}$ roll-off. DIBL falls exponentially with $L/\lambda$.⁵
• Degraded SS. The source and drain pin part of the barrier, so $\partial E_{\mathrm{peak}}/\partial E_{\mathrm{b,gate}}$ drops below 1 and SS rises above $m \times 60\,\mathrm{mV/dec}$.
• Punch-through. When the tails overlap completely, no barrier is left and the gate cannot turn the device off.

For a single gate over a channel (or depletion region) of thickness $t_{\mathrm{ch}}$ and oxide $t_{\mathrm{ox}}$, the classic approximation is

and the minimum usable channel length is a multiple of it, about $3\lambda$ for planar bulk.⁵ A second gate on the far side of a thin body shortens $\lambda$ further, which shows up in the UC Berkeley design rules of thumb: $t_{\mathrm{Si}}$ below $L_{\mathrm{g}}/4$ for single-gate ultra-thin-body SOI and below $2L_{\mathrm{g}}/3$ for double-gate devices.⁴ Every architecture in the next section is a way to make $t_{\mathrm{ch}}$ smaller or put more gate around it.

Planar bulk and the doping trap

In planar bulk the “channel thickness” in $\lambda$ is effectively the depletion depth, which can only be cut by raising the channel doping. That raises $m$ (worse SS), lowers mobility and, because a small gate covers few dopant atoms, adds random dopant fluctuation to $V_{\mathrm{T}}$.⁴ Ultra-thin-body SOI fixed the geometry directly (the body is physically thin, so it can be undoped), and multigate devices put a second gate on the far side of that body.

FinFET design

The vertical thin-body idea goes back to Hitachi’s DELTA transistor, published in 1990; Berkeley’s 1998 FinFET made it a self-aligned double gate that a planar-style process could build.⁴

A FinFET is a double gate (two sidewalls) or tri-gate (plus the top) device on a body of width $W_{\mathrm{fin}}$. The fin width sets DIBL; Berkeley’s data put the requirement at $L_{\mathrm{g}}/W_{\mathrm{fin}}$ above about 1.5.⁴ For DIBL of 100 mV/V, published design curves need $W_{\mathrm{Si}} \approx L_{\mathrm{g}}/2$ for a FinFET versus $H_{\mathrm{Si}} \approx L_{\mathrm{g}}/5$ for single-gate UTB SOI; tri-gates relax both somewhat.⁴ Other consequences:

• Quantized width. Effective width per fin is about $2H_{\mathrm{fin}} + W_{\mathrm{fin}}$, so drive comes in fin increments and fin height becomes a process-wide trade between layout efficiency and design flexibility.⁴ ASAP7’s 7.5-track cell allows at most three fins per nMOS and pMOS device.⁶
• Sub-fin leakage. On bulk wafers the fin’s base, below the gated region, needs a punch-through stopper (super-steep retrograde well).⁴
• $V_{\mathrm{T}}$ by work function. With undoped fins, threshold flavors come from gate work-function engineering rather than channel implants. ASAP7’s four flavors (SLVT, LVT, RVT, SRAM) share one drawn gate length and differ mainly in work function; the SRAM device also drops the lightly doped drain implant.⁶
• Variability. Performance becomes sensitive to fin width, and work-function variation replaces dopant fluctuation as the main $V_{\mathrm{T}}$ variation source in undoped channels.⁴
• Parasitics. Gate-to-source/drain fringing capacitance and series resistance in the narrow fin grow in importance as $L_{\mathrm{g}}$ shrinks.⁴

Nanosheets

Stacked nanosheets go further on both $\lambda$ knobs: the sheet thickness is set by growing the Si/SiGe layers rather than by etching a fin, and the gate covers the bottom face, closing the sub-fin path that a FinFET leaves connected to the body.⁸ The width becomes a layout parameter again, but the total stack height, the sheet count, the inner spacers between gate and source/drain and the n-p spacing in the cell now bound what you can draw. Variants trim the n-p spacing: the forksheet puts a dielectric wall between the n and p sheet stacks, and imec expects it to carry the nanosheet roadmap to around its A10 node.¹¹

Fins and nanosheets goes further on the devices: width per footprint, capacitance, self-heating, the inner-spacer and release modules, and how brand names map to these types.

CFET

A CFET stacks the n and p nanosheet stacks vertically. Two integration routes compete: monolithic, where top and bottom channels come from one epitaxial superlattice and are processed together, and sequential, where the top layer is bonded onto a finished bottom tier.¹⁰ Either way the process has to isolate the top device from the bottom one, give each its own gate work function, and reach the bottom source/drain without going through the top device. imec’s answer is to contact the bottom pFET directly from the backside; its IEDM 2025 work combines a frontside-contacted (100) nFET on top with a backside-contacted (110) pFET below, choosing crystal orientations that suit each carrier type.¹¹ The density case is cell height: with n-p spacing gone, imec targets cells of about four metal tracks.¹⁰ The 2023 IEDM demonstrations (Intel at 60 nm CPP with three sheets per device and a backside contact; Samsung at 48 and 45 nm CPP; TSMC at 48 nm with a high-germanium SiGe isolation layer) show the pieces working, but not yet at product yield.⁹

Backside power

Frontside power delivery spends cell height on wide $V_{\mathrm{DD}}$/$V_{\mathrm{SS}}$ rails and at least a fifth of the routing on the power grid, while the resistance of thin lower-metal vias and wires grows each node.¹² imec’s flow uses buried power rails (metal lines sunk into the front-end, below the devices) connected by nano-TSVs to a backside network after carrier bonding and thinning to a SiGe etch stop; the test vehicle cut IR drop 7×.¹² Intel’s PowerVia drills its nano-TSVs from the front and exposes them by thinning; its test core reported more than 6% frequency gain, 30% lower delivery loss and local cell utilization up to 95%, with new thermal design and debug methods required.¹³ For CFET, backside access stops being optional: the bottom device’s source/drain is reached from below.⁹

For physical design this changes the cell template (no frontside rails), the PDN (no power straps competing with signals in the BEOL), IR-drop and electromigration signoff, and debug, which needed new methods in Intel’s test chips.¹³ See the Power planning and Routing stages.

Node names were once both the gate length and the metal half-pitch, which for a long time were about the same number, and each generation cut features by about 30% to double density. From the mid-1990s gate length was scaled ahead of pitch for performance (the 130 nm node shipped 70 nm gates), and in the FinFET era the opposite: electrostatics held $L_{\mathrm{g}}$ near 20–26 nm while the label kept falling.¹⁴ Intel’s 22 nm FinFETs (2011) had 26 nm gates, a 40 nm half-pitch and 8 nm fins.¹⁴ ASAP7’s “7 nm” has a 21 nm physical gate on a 54 nm CPP and 36 nm M1–M3 pitch; the authors deliberately relaxed CPP, noting that a larger pitch eases pin access and can give better logic density at iso-power and performance.⁶

To first order, cell area = CPP × (cell width in gate pitches) × $\mathrm{M}_x$ pitch × (track height), divided by device tiers. That’s why IRDS’s G-M-T notation (G48M36T1 for “5 nm”) captures density where the node name can’t, and why much of each generation’s density gain now comes from DTCO moves that reduce track height or gate pitches per cell (fewer fins per device and fewer tracks, tighter diffusion breaks, buried or backside power rails, stacked devices) rather than from $L_{\mathrm{g}}$.¹⁴⁶¹² The alternative “LMC” metric reports the density of logic, of main memory and of the interconnect linking them.¹⁴

A quasi-2D natural-length model: $\lambda$ from $t_{\mathrm{ch}}$, EOT and an effective gate count $N$ per architecture; the off-state conduction band $E_{\mathrm{c}}(y)$ from the 1D screened Poisson solution; SS from the gate’s leverage on the barrier peak, DIBL from the peak’s drain dependence, $I_{\mathrm{off}}$ from the peak height. The FinFET case is calibrated so that at $L = 21\,\mathrm{nm}$ it lands near ASAP7’s predictive RVT nFET. The full model is shown below the plot.

ASAP7 is predictive: its assumptions were derived from published 14–10 nm data and trends, it isn’t tied to any foundry, and its authors note it will be inaccurate in some details.⁶ Its electrostatic targets were explicit: SS approaching the 60 mV/dec limit and DIBL around 30 mV/V, “following the best to date FinFET published result,” both eased by the relaxed 54 nm CPP allowing a longer gate.⁶

Fins 32 nm tall and 6.5 nm thick on a 27 nm pitch; $L_{\mathrm{g}}$ 21 nm (20 nm drawn); CPP 54 nm; M1–M3 36 nm pitch, single-patterned EUV; M4–M5 48 nm and M6–M7 64 nm with self-aligned double patterning; $V_{\mathrm{DD}}$ 0.7 V.⁶

Points worth noticing in the table:

• $I_{\mathrm{off}}$ rises 10–19× per $V_{\mathrm{T}}$ flavor step while $V_{\mathrm{T,sat}}$ drops 60–80 mV, which is what an SS near 63 mV/dec predicts. $I_{\mathrm{eff}}$, the inverter-relevant drive, is roughly half of $I_{\mathrm{dsat}}$.
• The $V_{\mathrm{T,lin}} - V_{\mathrm{T,sat}}$ difference (0.02 V for the RVT nFET) is consistent with $\mathrm{DIBL} \times (0.7 - 0.05)\,\mathrm{V} \approx 14\,\mathrm{mV}$, given the table’s 10 mV rounding.
• PMOS drive is about 90% of NMOS, an assumption the authors base on strain trends from 32 nm planar to 14 nm FinFETs.⁶
• The gear ratio between the 27 nm fin pitch and the 36 nm M2 pitch gives whole numbers of fins at 6, 7.5, 9 and 12 tracks; ASAP7 chose 7.5 tracks (270 nm) with up to three fins per device.⁶

For cell layouts built on these rules, see From devices to a cell library; for how the 27 nm fins and 36 nm EUV wires are printed, see Making them.

• Electrostatics vs parasitics. Multigate devices win SS and DIBL but pay in gate-to-source/drain fringing capacitance and in series resistance through narrow fins, and series resistance matters more as $L_{\mathrm{g}}$ shrinks.⁴
• Relaxed pitch vs density. ASAP7 deliberately chose a less aggressive CPP for low power and short-channel control, citing DTCO results where a larger transistor pitch improved pin access and gave better logic density at iso-power and performance.⁶
• Width quantization vs SRAM stability. FinFET SRAM cells come in fin-count ratios (1-2-3, 1-1-2, 1-1-1); the densest 1-1-1 cell needs read and write assist circuits.⁶ See Memory cells.
• Variability. Undoped channels remove random dopant fluctuation but expose fin-width and work-function variation; below about 10 nm, source/drain dopant gradients trade performance against variability.⁴
• Backside: wins and new failure modes. Backside power frees routing and cuts IR drop, but adds wafer bonding and thinning, changes the thermal path, and required new debug methods.¹³
• CFET integration risk. Top/bottom isolation, separate n and p gate stacks and bottom-device contacts all have to work in one stack at product yield; in 2023, estimates put production 7–10 years out.⁹
• The model’s limit. Scale-length scaling has a floor: for atomically thin channels, published simulations find $\lambda$ set by the physical oxide thickness, not by the channel.⁵

The natural-length model, step by step

Take the off state of an n-channel device with source at $y = 0$ and drain at $y = L$. Write the channel potential as the long-channel value set by the gate plus a correction that satisfies the source and drain boundary conditions. Gauss’s law on a thin slice of channel, with the vertical field approximated as linear through the body and oxide, turns the 2D Poisson equation into

whose solution decays from each junction as $\sinh(y/\lambda)$. This is the screening-length picture behind the $\exp(-L/\lambda)$-type dependence of DIBL.⁵ In energy terms, with $E_{\mathrm{b}}$ the long-channel barrier and the drain at $-qV_{\mathrm{D}}$:

The barrier peak $E_{\mathrm{peak}}$ sets the off-current, $I_{\mathrm{off}} \propto \exp(-E_{\mathrm{peak}}/kT)$. Three figures of merit follow directly:

1. SS $= 60\,\mathrm{mV/dec} \cdot m/g$, with $g = \partial E_{\mathrm{peak}}/\partial E_{\mathrm{b}}$. Long channel: $g = 1$. Short channel: the junctions pin part of the barrier and $g < 1$.
2. DIBL $= \big[E_{\mathrm{peak}}(V_{\mathrm{D,lin}}) - E_{\mathrm{peak}}(V_{\mathrm{DD}})\big] / (V_{\mathrm{DD}} - V_{\mathrm{D,lin}})$.
3. $I_{\mathrm{off}}$ $= I_0 \cdot 10^{-(E_{\mathrm{peak}} - E_{\mathrm{th}})/60\,\mathrm{mV}}$, where $E_{\mathrm{th}}$ is the barrier at threshold and $I_0$ the constant-current threshold definition.

For $L \gg \lambda$ the peak is near the middle and the lowering is approximately

so roll-off, DIBL and SS degradation all decay as $\exp(-L/2\lambda)$. Doubling $L/\lambda$ squares the suppression factor. In this model, for a given body factor, the shortest usable $L$ is roughly a fixed multiple of $\lambda$ (about $4\lambda$ for FinFET and GAA here; planar needs about $5\lambda$ because its $m = 1.25$ already costs SS), so an architecture that cuts $\lambda$ by 30% allows a 30% shorter gate, about one traditional generation.

$\lambda$ for each architecture

For a single gate, $\lambda \approx \sqrt{\varepsilon_{\mathrm{Si}}\, t_{\mathrm{ch}}\, t_{\mathrm{ox}} / \varepsilon_{\mathrm{ox}}}$ with $t_{\mathrm{ch}}$ the body or depletion thickness.⁵ The sim extends it to multigate devices in the simplest way, by dividing the term under the root by an effective number of gated sides $N$. That is a modeling choice for illustration, not a derived result. Its inputs ($\varepsilon_{\mathrm{Si}}/\varepsilon_{\mathrm{ox}} \approx 3$):

“Usable” here means $\mathrm{SS} \le 90\,\mathrm{mV/dec}$ and $\mathrm{DIBL} \le 100\,\mathrm{mV/V}$. The 100 mV/V DIBL figure is the target used in published multigate design curves.⁴ The model is optimistic about absolute lengths (real processes keep margin for variation, parasitic resistance and leakage targets), but the ordering and the ratio are the point. At $L = 21\,\mathrm{nm}$ the FinFET case gives $\mathrm{SS} \approx 64\,\mathrm{mV/dec}$ and $\mathrm{DIBL} \approx 22\,\mathrm{mV/V}$, close to ASAP7’s predictive RVT nFET (63.0 mV/dec, 21.3 mV/V).⁶

Assumptions and what the model leaves out

• One-dimensional reduction: vertical fields linear through body and oxide; fringing fields through the spacers ignored. Quantitatively wrong for $L$ below about $3\lambda$, which the sim flags.
• Boltzmann statistics and drift-diffusion: no source-to-drain tunneling (significant below about 10 nm), no quantum confinement shift of $V_{\mathrm{T}}$ in very thin bodies.
• The bulk body factor $m$ is a constant, not a function of doping and bias; $N$ is an effective number, not derived from a 3D solution.
• Off-state only: no velocity saturation, series resistance or mobility, so it says nothing about $I_{\mathrm{on}}$. The I-V curve chapter covers the on state.
• At atomic-scale channel thickness, $\lambda$ saturates at a value set by the physical oxide thickness.⁵

How production models handle it

Compact models used in real kits fold the same physics into fitted parameters. ASAP7’s transistors use BSIM-CMG, a compact model for multigate devices, with parameters derived from public data and historical trends.⁶ Compact models fit short-channel behavior with parameters extracted from measurements or device simulation, so they track SS and DIBL across gate lengths far more closely than a hand formula like this one.