Making them

The device physics in the earlier chapters assumes structures that someone has to build, at a cost and with a yield. This chapter covers the build: the unit processes, how they are sequenced into a CMOS flow of hundreds of steps (up to about 1,400 for the most complex processes), how the fab keeps each step on target, and the yield and cost arithmetic that turns defect density and die area into a price per good die.²

Three constraints run through everything:

• Lithography pitch decides which layers need extreme ultraviolet, which need multiple patterning, and why modern layouts are so regular.
• Thermal budget decides the order of steps: hot steps first, and anything that can’t take heat later.
• Defectivity decides yield, and through it the economics of large dies.

Two open process kits anchor the numbers. SKY130 is a mature 180–130 nm-class planar process with five metal levels.²⁹ ASAP7 is a predictive 7 nm FinFET kit whose design rule manual states, for every layer, whether it is printed with 193 nm immersion or EUV and whether it is single-exposed or multi-patterned.¹⁴ The After tapeout page covers masks, the Rayleigh resolution limit, wafer sort and the yield-learning loop. This chapter links to it instead of repeating it.

A CMOS start wafer is typically lightly doped p-type (100) silicon, around $10^{15}\,\mathrm{cm^{-3}}$.⁵

The edge matters more than its area suggests. Deposited film thickness is well controlled across the center but poorly controlled near the edge, so edge dies fail wholesale. Because inline inspection and parametric test usually skip edge dies, that loss shows up as die yield loss even though random defects don’t cause it.⁶ Fabs write off an edge-exclusion ring (the simulation below uses 3 mm, an illustrative value), and yield models must separate this position-dependent loss from random defects.

Cycle time is a design input too. About 12 weeks in the fab on average, and 14–20 weeks for advanced processes,² means a process change, or a respin, takes a quarter or more to show results. It is also why inline measurement, not end-of-line test, is the fab’s main feedback loop.

The After tapeout page derives $R = k_1 \lambda/\mathrm{NA}$ and tabulates single-exposure pitch limits. Here the question is how those limits shape a real layer stack. The ASAP7 design rule manual assigns each layer a lithography and a patterning scheme:¹⁴

Read the table from the pitch constraints. Spacer patterning halves pitch per round without a second critical alignment, so a 27 nm fin pitch by SAQP starts from a 108 nm mandrel, and a 54 nm gate pitch by SADP also starts from 108 nm. Both mandrels sit above the 75–80 nm practical single-exposure limit of immersion.⁹ Spacer patterning forces every line to the same width and needs extra trim (cut) steps,¹⁰ which is why FinFET layouts are fins and gates on fixed pitches. The irregular part of the pattern moves into cut layers, ACTIVE and GCUT, which ASAP7 assigns to EUV.¹⁴

For EUV at NA 0.33 the $0.5\,\lambda/\mathrm{NA}$ bound gives about 20 nm pitch, but practice stops well short of it. When imec printed test patterns at the 32 nm interconnect pitch of a 5 nm process, it found stochastic defects: bridges between lines, missing holes and merged holes.¹⁵ ASAP7’s 36 nm M1 pitch sits just above that. LELE needs much tighter mask-to-mask overlay, while spacer schemes are self-aligned and need about the same overlay as a single exposure.¹⁰ ASAP7 uses LELE only for the V4–V7 via layers.¹⁴

Two physical effects drive the choice between EUV and immersion:

• Photon count. A 13.5 nm photon carries about $193/13.5 \approx 14$ times the energy of a 193 nm photon. At equal dose, a feature therefore receives about 14 times fewer photons. Deep-UV and EUV resists are chemically amplified: each absorbed photon releases an acid that, during the post-exposure bake, catalyzes many deprotection reactions.¹⁶¹² So the randomness of photon arrival and of the resist chemistry shows up directly as line-edge roughness and occasional missing or merged features.¹⁵¹²
• Depth of focus. In the simple Rayleigh model, depth of focus scales as $k_2 \lambda/\mathrm{NA}^2$.¹⁷ Raising NA from 0.33 to 0.55 shrinks it by roughly $(0.55/0.33)^2 \approx 2.8\times$, which tightens the flatness every polish step must deliver. High-NA tools also halve the exposure field: the optics shrink the image more in one direction only, because shrinking it more in both would have cut throughput below 100 wafers per hour.¹¹

Each unit process is a set of trade-offs, and integration is mostly about stacking them so that one step’s side effects don’t break another.

Etch: anisotropy against selectivity

Physical sputtering by Ar⁺ transfers momentum on every collision, so its sticking coefficient is near 1 and it is anisotropic, but it hardly distinguishes one material from another. Chemical etching by radicals such as F and Cl is selective, but radicals need several steps to react, giving effective sticking coefficients near 0.01. They bounce and etch sidewalls, so the result is isotropic. Reactive ion etching uses ion bombardment to enhance chemical etching only on surfaces facing the plasma. Lowering pressure to 10–100 mTorr lengthens the ion mean free path and raises anisotropy.²⁰ Every patterning step therefore needs a stop layer that etches much slower, such as the nitride under STI fill or the thin dielectric under the gate. That is why so many films in a flow exist only to be etched against and then removed.

Thermal budget

Dopant profiles move whenever the wafer is hot, so the flow is ordered by temperature. Older twin-well processes drove wells 2–3 µm deep with more than 8 hours above 1050 °C. Retrograde wells replace that with high-energy implants whose profile peaks below the surface, giving lower well resistance and less lateral spread.⁵ The activation anneal itself trades crystal repair against dopant diffusion, which is why source/drain activation uses rapid thermal annealing.²² The same logic later forces the gate-last flow described in the next section.

Conformal films

ALD’s self-limiting chemistry gives thickness set by cycle count and conformal coverage of high-aspect-ratio features, and hafnium oxide for transistor gate dielectrics is one of its standard films.¹⁹ In nanosheet transistors it fills recesses only a few nanometers deep between stacked channels, chosen for its gap-filling ability.³²

Polish

CMP removes material by height rather than through a mask. Film thickness varies, so some overpolish is always needed, and overpolish dishes soft fill material and erodes the surface around it.²³ Flows design around this with stop layers: STI fill polishes down onto a nitride hard mask, which is then stripped.⁵ Dishing and erosion vary with the pattern underneath, which is the physical reason for the density windows in the GDS & tapeout chapter.

Gate-last high-κ/metal gate

A metal gate can’t simply replace polysilicon in the flow above. Source/drain activation needs anneals above 900 °C, which can degrade a metal gate or make it react with the dielectric.³¹ The gate-last (replacement-gate) flow keeps a polysilicon dummy gate through the hot steps:

1. Deposit the high-κ dielectric, build a polysilicon dummy gate on it, and form the self-aligned sources and drains around it.
2. Deposit an interlevel dielectric and polish it down to the top of the dummy gate.
3. Etch out the dummy gate.
4. Fill the trench with metal, with different work-function metals for NMOS and PMOS.¹³¹

Threshold voltage is then set by work-function metal and by masked threshold-adjust steps. ASAP7 lists separate SLVT, LVT and SRAM threshold masks among its front-end layers.¹⁴ Each extra threshold flavor a library offers costs masks and steps.

FinFET and nanosheet modules

In a FinFET flow, the fins are a SAQP grating at 27 nm pitch in ASAP7, trimmed by an EUV ACTIVE layer. The gates are a SADP grating at 54 nm pitch, cut by GCUT. Above them, the MOL is three EUV layers: gate interconnect (LIG), source/drain interconnect (LISD) and V0 up to M1.¹⁴

Gate-all-around nanosheets reuse much of the FinFET integration. Three modules are new:³²

• The superlattice. Epitaxy grows alternating Si and SiGe layers.
• The inner spacer. The SiGe ends are recessed laterally and refilled with dielectric. This cuts gate-to-source/drain capacitance and protects the source/drain epitaxy.
• Channel release. The remaining SiGe is etched away selectively so the gate can wrap the silicon sheets.

The tolerances are tight: one study reports SiGe cavity depths held to $\le 5 \pm 0.3\,\mathrm{nm}$ across the stack.³² The Shrinking chapter covers why these shapes win electrostatically. Here the point is that each new device shape arrives as a handful of new, very selective etch and deposition modules inside an otherwise familiar flow.

Two kits, two eras

SKY130’s 34 masks include a local-interconnect layer between contacts and M1, and five metals.³⁰²⁹ ASAP7’s FEOL, MOL and BEOL tables list 33 drawn layers through nine metals and the pad. Its fin, gate, M4–M7 and V4–V7 layers are multi-patterned, so the physical mask count is higher than the layer count.¹⁴ For every extra patterning pass, the price is coat, expose, develop, etch, clean and metrology steps, plus another overlay budget.

Fab data is hierarchical, and that shapes how it is charted. The NIST/SEMATECH handbook’s lithography case study measures line width at 5 sites per wafer, on 3 wafers per cassette, across 30 cassettes: 450 measurements.³⁵ The largest variance component is lot to lot. A Shewhart chart with limits from within-lot variation therefore flags lots whose shift already has a known, assignable cause. Yet the measurement of interest is still the site level.³⁶ One remedy it discusses is to chart each nested source at its own level, at the cost of more charts.³⁶ In variance terms, $\sigma_{\mathrm{total}}^2 = \sigma_{\mathrm{lot}}^2 + \sigma_{\mathrm{wafer}}^2 + \sigma_{\mathrm{site}}^2$. Separating the components tells engineers whether to look at what changes between lots, between wafers in a lot, or across a single wafer.

Yield data then splits loss by its signature. Leachman writes die yield as $\mathrm{DY} = Y_{\mathrm{S}} \cdot Y_{\mathrm{R}}$. $Y_{\mathrm{R}}$ is the random, defect-limited yield, which only cleaner processes and tools raise. $Y_{\mathrm{S}}$ is the systematic-limited yield, from mechanisms with spatial or lot signatures such as edge loss, which better process execution and process control fix.⁶ The After tapeout page follows the loop from there into wafer maps, scan diagnosis and failure analysis.

Overlay deserves its own budget. With LELE, two masks on the same layer must register to each other as well as to the layers below.¹⁰ At sub-nanometer tolerances every contributor counts: the scanner, the masks, the process steps that distort the wafer, and the measurement itself.³³

The cross-section is an eight-state model of a planar CMOS inverter flow, with the module (FEOL, MOL, BEOL) and a recipe line for each step. A particle dropped at a step maps to that step’s failure mode: a blocked STI etch (leakage), a well-implant shadow (benign), a gate-dielectric inclusion (latent), an etch-masking stub, a blocked p+ implant, a blocked contact (open), or an M1 bridge (short).

The yield panel counts whole dies by placement, not by formula, and shows the formula estimate $\pi (d/2)^2/A - \pi d/\sqrt{2A}$ alongside. Try these:

• Switch between Poisson, Murphy and negative binomial. Failing dies are drawn clustered for the compound models.
• At 600 mm² and $D_0 = 0.5$, compare 5.0% (Poisson) with 10.0% (Murphy) and 12.5% (negative binomial, $\alpha = 3$).
• Push $\alpha$ toward 10 and watch the negative binomial converge on Poisson.

Historical die economics

Baas’s lecture notes tabulate 1994 parts, all on wafers costing $900–$1,700:³⁷

A 7× increase in area gave a roughly 100× increase in die cost. Defect densities of 1–1.5 per cm² were survivable only because dies were small, and the yields in this table sit well above the Poisson prediction. At 296 mm² and 1.5 cm⁻², Poisson gives $e^{-4.4} \approx 1.2\%$, against 9% reported. That gap is what the clustered models in Under the hood account for.

Patterning cost by layer (ASAP7)

Of ASAP7’s 33 drawn layers, the FEOL has 11, the MOL 3, and the BEOL 19 (M1–M9, V1–V9 and the pad).¹⁴ The patterning breaks down like this:

• EUV single exposure: 12 layers (ACTIVE, GCUT, SDT, the 3 MOL layers, M1–M3 and V1–V3).
• 193i SAQP: 1 layer (FIN).
• 193i SADP: 5 layers (GATE, M4–M7).
• 193i LELE: 4 via layers (V4–V7).
• 193i single exposure: the rest.

Spacer layers also need cut or block masks, and LELE layers need two exposures, so the mask count exceeds the layer count. Lithography tool prices went from $450,000 in 1979 to $123 million in 2019.¹³ This is why mask and exposure count, not layer count, drives wafer cost at leading nodes.

Regularity against freedom

Spacer patterning buys pitch with perfectly periodic gratings and moves the design freedom into cut layers.¹⁰¹⁴ The cost lands in the cell library: fixed gate and fin pitches, unidirectional low metals, and coloring rules on multi-patterned layers. The cell library chapter picks this up.

Thermal budget against materials

Gate-last high-κ/metal gate exists because a metal gate can degrade in the source/drain activation anneal.³¹ The price is extra deposition, polish and etch modules, and work-function metals that must fit into ever-narrower replacement trenches. Each new channel material or backside-power scheme reopens the same question of what can be hot, and when.

Model choice against risk

The same $D_0$ gives very different large-die yields under different models: at 600 mm² and 0.5 cm⁻², 5% (Poisson) against 10% (Murphy) and 12.5% (negative binomial, $\alpha = 3$). Yield models are valid where they were fit. Poisson is accurate for small dies, about 0.25 cm² or less, and for $D_0 A$ below 1. It underestimates yield for large dies because defects cluster.⁶ Pricing a large die with a Poisson $D_0$ fitted on small test chips is pessimistic. Pricing it with an assumed $\alpha$ nobody has measured can be optimistic.

Failure modes the models miss

• Latent defects. A particle in the gate dielectric may pass every test and fail in the field. This is the reliability side of the After tapeout page.
• Stochastic defects. EUV missing or merged features don’t come from particles, so particle-based $D_0$ doesn’t capture them, and they become a problem as pitch shrinks.¹⁵
• Systematic, layout-dependent failures. Lithography hotspots and CMP-sensitive patterns repeat in every die with that pattern and land in $Y_{\mathrm{S}}$, not $D_0$.⁶

The Poisson yield model and per-layer defect budgets

If killer defects land independently with mean $\lambda = D_0 A$ per die, the chance a die has $k$ defects is $\lambda^k e^{-\lambda}/k!$. A die works only with $k = 0$, so $Y = e^{-D_0 A}$. Inverting gives $D_0 = -\ln(Y)/A$, which is how fabs quote defect density from observed yield.⁶ The useful property is additivity. If $D_0 = D_1 + D_2 + \dots + D_n$ over layers or steps, then $Y = \prod_i e^{-D_i A}$. So the yield gain from cutting one layer’s defectivity by $\Delta D_j$ is simply a factor of $e^{\Delta D_j A}$.⁶ That is how a fab turns inline inspection counts per layer into a yield budget.

Compound Poisson: Murphy, Seeds and negative binomial

Real defect density varies from die to die, wafer to wafer and lot to lot. Murphy’s idea was to average the Poisson yield over a distribution $f(D)$ with mean $D_0$:⁶

• Uniform $f$ on $[0, 2D_0]$ gives $Y = (1 - e^{-2D_0 A})/(2D_0 A)$.
• A triangular $f$ on $[0, 2D_0]$, peaking at $D_0$, gives the Murphy model, $Y = \big((1 - e^{-D_0 A})/(D_0 A)\big)^2$.
• An exponential $f$ gives Seeds’ model, $Y = 1/(1 + D_0 A)$.
• A gamma $f$ gives the negative binomial, $Y = (1 + D_0 A/\alpha)^{-\alpha}$, where $\alpha$ is the cluster parameter. $\alpha$ can be estimated from the mean and standard deviation of defect counts per die.⁶

The negative binomial spans the others. With $\alpha$ of about 10 or more it is essentially Poisson, with $\alpha = 5$ it approximates Murphy, and with $\alpha = 1$ it approximates Seeds.⁶ Baas’s course notes use $\alpha \approx 3$ for modern CMOS.³⁷

Why does clustering raise yield? $e^{-DA}$ is convex in $D$, so by Jensen’s inequality the average of $e^{-DA}$ over any spread of $D$ is at least $e^{-D_0 A}$. Concentrating defects on some dies spares others. The effect is negligible when $D_0 A$ is small and large when $D_0 A$ is several. In the simulation, a 600 mm² die at 0.5 cm⁻² ($\lambda = 3$) gives 5.0% under Poisson, 10.0% under Murphy and 12.5% under the negative binomial with $\alpha = 3$. A 100 mm² die ($\lambda = 0.5$) gives 60.7%, 61.9% and 63.0%.

Systematic loss multiplies on top: $\mathrm{DY} = Y_{\mathrm{S}}\, e^{-D_0 A}$. Fitting $\ln \mathrm{DY}$ against $A$ across die sizes gives $\ln Y_{\mathrm{S}}$ as the intercept and $-D_0$ as the slope.⁶ The windowing method on the After tapeout page generates those different sizes from one product’s wafer map.

Dies per wafer

The textbook estimate is $\mathrm{DPW} \approx \pi (d/2)^2/A - \pi d/\sqrt{2A}$.³⁷ The first term is wafer area over die area. The second is a correction for edge loss: the circumference $\pi d$ divided by $\sqrt{2A}$, the diagonal of a square die. Roughly one die is lost per diagonal-length of edge. For $d = 300\,\mathrm{mm}$ and $A = 100\,\mathrm{mm^2}$, it gives $707 - 67 \approx 640$.

The simulation instead places square dies on a grid with 0.1 mm scribe lanes. It keeps only dies that lie wholly inside a 147 mm radius (3 mm edge exclusion) and tries four grid offsets, keeping the best. That gives 616 at 100 mm², a little below the formula because of the exclusion ring and scribe lanes. Real die counts also lose sites to test structures and alignment marks.

Cost per good die

$\text{Die cost} = \text{wafer cost} \div (\mathrm{DPW} \times Y)$.³⁷ Both factors in the denominator fall with area: $\mathrm{DPW}$ roughly as $1/A$, and $Y$ exponentially in Poisson or as a power in the negative binomial. So die cost rises much faster than area. Baas’s notes summarize it as a steep function of die area, of order $A^4$, for the defect densities of the day.³⁷ The exponent isn’t a law. It depends on $D_0 A$: for small, mature-process dies, cost is close to linear in area, and the super-linear penalty only bites once $D_0 A$ approaches 1. Package, test and assembly yield multiply on top, which is the argument for known-good-die testing in multi-die products.

Spacer patterning, step by step

1. Print a mandrel grating at pitch $P$ with one immersion exposure.
2. Deposit a conformal film of thickness $t$, then etch it anisotropically. Material remains only on the mandrel sidewalls.
3. Remove the mandrel. Two spacer lines now sit in every pitch $P$, so the pitch is $P/2$.
4. For SAQP, use those spacers as the next mandrel and repeat, giving $P/4$.

Line width is set by the spacer film, not by lithography, which is why spacer-defined fins are so uniform and every line has the same width. Line placement depends on the mandrel’s CD and the spacer thickness, not on a second critical alignment.¹⁰ The catch is that the result is a uniform grating. Ends, gaps and jogs need cut masks, which ASAP7 puts on EUV (ACTIVE for fins, GCUT for gates). Its 27 nm fins from a 108 nm mandrel and 54 nm gates from a 108 nm mandrel follow directly.¹⁴

Control limits for nested data

A Shewhart chart puts its center line at the in-control mean and its limits at $\pm 3\sigma$, where $\sigma$ is the standard deviation of the plotted statistic.³⁴ With nested sampling, the plotted statistic’s variance depends on what is plotted. Lot means of $n_w$ wafers × $n_s$ sites have variance

If the limits are computed only from the within-lot terms and $\sigma_{\mathrm{lot}}^2$ dominates, many lots fall outside the limits even though their variation is normal for the process, and engineers learn to ignore the chart. Charting each level separately, one of the options the NIST case discusses, avoids that.³⁶