CMOS logic

Given a MOSFET as a switch with a threshold, an on-resistance and a gate capacitance (the switch), static CMOS builds every gate from two complementary networks: an NMOS pull-down network (PDN) to GND and a PMOS pull-up network (PUN) to $V_{\mathrm{DD}}$, with the PUN the series/parallel dual of the PDN.² Duality guarantees that for every input vector exactly one network conducts: no contention (both on, the “crowbar” state) and no floating output (both off). The properties designers rely on fall out of that:

• Rail-to-rail levels. The conducting network ties the output all the way to $V_{\mathrm{DD}}$ or GND, so $V_{\mathrm{OH}} = V_{\mathrm{DD}}$ and $V_{\mathrm{OL}} = 0$ with no static load.³
• Ideally zero static current. No DC path exists in either logic state. What is left is leakage, which is far from negligible at nanometer nodes.⁹
• High gain around the switching point, which makes logic levels regenerate stage after stage.⁵
• Inverting stages only, and $2n$ transistors for an $n$-input gate.

Historically the alternative was ratioed NMOS logic. A resistor pull-up forces a trade between noise margin and speed, and a current-source pull-up that eases the trade still burns current whenever the output is low.³ CMOS, presented by Sah and Wanlass in 1963, won once processes caught up in performance, because it offered the best way to manage power density as integration grew.¹ This chapter covers the DC side: topology, the transfer curve, noise margins, P/N sizing and fan-in. Delay and energy get their own chapter in Speed and power.

Networks and duality

A static CMOS gate computes $Y = \overline{f(x)}$, where $f$ is the conduction function of the PDN: series composition is AND, parallel is OR, over uncomplemented inputs. The PUN, built from PMOS that conduct on 0, must conduct exactly when $f$ is false. By De Morgan, $\overline{f(x)}$ evaluated on PMOS (which see $\overline{x}$) is $f$ with AND and OR swapped, so the PUN is the series/parallel dual of the PDN.² Consequences worth keeping in mind:

• Two failure states are excluded by construction. Both networks on is contention (a “crowbar” DC path whose output level is set by a resistive divider); both off is a floating, high-Z output.² Any non-dual network, for example from a schematic error or a missing transistor, creates one of these for some input vector.
• Transistor count is $2n$ for an $n$-input single-stage gate, one NMOS and one PMOS per input.
• Series depth is split between the networks. NAND puts its depth in the NMOS stack, NOR in the PMOS stack, and a complex gate trades them off (AOI21: PDN depth 2, PUN depth 2). Depth sets sizing, as the sizing section shows.

Why a single stage must invert

An NMOS passing a high level turns itself off when its source reaches $V_{\mathrm{DD}} - V_{\mathrm{Tn}}$ (and later than that, given body effect), so it delivers a degraded 1 and approaches it slowly; a PMOS cannot pull below $|V_{\mathrm{Tp}}|$.⁴ Restricting NMOS to the PDN and PMOS to the PUN keeps every transistor in its strong direction, with its source on a rail or on a stack node near one. Under that restriction a $0 \to 1$ input edge can only turn NMOS on and PMOS off, so each stage is a monotone-decreasing function of its inputs. Non-inverting functions cost a second stage. The SKY130 and2_1 is a 0.42 µm NAND2 driving a 0.65/1.0 µm inverter.¹⁶ That cost is why a technology mapper, choosing cells to cover a design’s logic, prefers inverting NAND, NOR and AOI/OAI cells where it can (see Logic synthesis).

Pass-transistor and transmission-gate styles break the rule on purpose. A transmission gate pairs an NMOS and a PMOS in parallel so the switch passes both levels fully.⁴ These styles are used for multiplexers and latches, but because their outputs are not driven from the rails, a chain of them does not restore levels the way a static CMOS gate does.

Complex gates in a real library

Compound gates implement any series-parallel inverting function in one stage.² Open libraries carry many of them. SKY130’s high-density library includes a21oi, a22oi, a211oi, a2111oi, o21ai, o22ai and a long list of other AOI/OAI variants alongside nand2–4 and nor2–4.¹⁸ Its a21oi_1 netlist shows the duality directly: NMOS A1–A2 in series and that pair in parallel with B1; PMOS $\mathrm{A1} \parallel \mathrm{A2}$ in series with B1.¹⁷

.subckt sky130_fd_sc_hd__a21oi_1 A1 A2 B1 VGND VNB VPB VPWR Y
X0 a_199_47# A2 VGND VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X1 a_113_297# A1 VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X2 Y B1 a_113_297# VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X3 VGND B1 Y VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X4 VPWR A2 a_113_297# VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X5 Y A1 a_199_47# VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
.ends

Regions of the inverter VTC

The DC transfer curve is the locus $I_{\mathrm{dsn}}(V_{\mathrm{in}}, V_{\mathrm{out}}) = |I_{\mathrm{dsp}}|(V_{\mathrm{in}}, V_{\mathrm{out}})$, most easily found by load-line analysis: overlay the NMOS and PMOS output curves for each $V_{\mathrm{in}}$ and read off the crossing.⁴ Classifying each device as off, linear or saturated gives five regions:⁴³

In region C both devices are current sources, so the slope is limited only by their output resistance: $A_{\mathrm{v}} = -(g_{\mathrm{mn}} + g_{\mathrm{mp}})(r_{\mathrm{on}} \parallel r_{\mathrm{op}})$, which can be large.³ In an ideal square-law device with no channel-length modulation the slope there is infinite; real short-channel devices have far lower output resistance, which makes region C less steep and eats into the noise margins (see The I-V curve for why).

Defining the levels

$V_{\mathrm{IL}}$ and $V_{\mathrm{IH}}$ are conventionally taken at the two unity-gain points (slope $-1$), with $V_{\mathrm{OH}} = V_{\mathrm{out}}(V_{\mathrm{IL}})$ and $V_{\mathrm{OL}} = V_{\mathrm{out}}(V_{\mathrm{IH}})$. Choosing the levels there maximizes the noise margins.⁴ The justification is regeneration: where $|\text{slope}| < 1$, a perturbation at the input shrinks at the output; where $|\text{slope}| > 1$ it grows. A chain of stages therefore drives any input outside $[V_{\mathrm{IL}}, V_{\mathrm{IH}}]$ to the rail.⁵ The simulator’s balanced inverter (square law, $V_{\mathrm{Tn}} = |V_{\mathrm{Tp}}| = 0.5\,\mathrm{V}$, $\lambda = 0.1\,\mathrm{V}^{-1}$, $V_{\mathrm{DD}} = 1.8\,\mathrm{V}$) gives $V_{\mathrm{IL}} \approx 0.78\,\mathrm{V}$, $V_{\mathrm{IH}} \approx 1.02\,\mathrm{V}$ and $\mathrm{NM}_{\mathrm{L}} = \mathrm{NM}_{\mathrm{H}} \approx 0.68\,\mathrm{V}$, about 38% of $V_{\mathrm{DD}}$.

What the margins have to absorb

Static noise margins budget DC-like disturbances: IR drop and ground bounce that shift a driver’s rails relative to a receiver’s, and coupling from switching neighbors.⁵ Coupling from an aggressor wire onto a quiet victim is crosstalk. The Cornell notes show that as feature sizes shrank, crosstalk glitches stronger than 80% could occur.⁵ A glitch that large exceeds any static margin. Whether it causes a failure then depends on how long it lasts and whether a flip-flop captures it, which a DC transfer curve cannot tell you.

Margins also shrink with $V_{\mathrm{DD}}$. With $V_{\mathrm{Tn}}$ and $|V_{\mathrm{Tp}}|$ roughly fixed, lowering the supply shrinks the region where both devices conduct and lowers the gain, so near-threshold logic trades margin for energy. The trade is quantified in Speed and power.

The RC view of sizing

Model an on transistor as a resistor inversely proportional to width. With a unit NMOS of resistance $R$, a unit-width PMOS has about $2R$, from the mobility ratio.⁴ The ratio $\mu$ is 2–3 in classic planar processes.⁷ Sizing for equal drive then means: every path through the PDN totals $R$ and every path through the PUN totals $R$. A device in a $k$-high stack is therefore sized $k$ (NMOS) or $k\mu$ (PMOS) units wide:

Input capacitance relative to the inverter’s 3 is the logical effort: 4/3 for NAND2 and 5/3 for NOR2, and in general $(n+2)/3$ for an $n$-input NAND and $(2n+1)/3$ for NOR.⁶ Effort is the price of the function; the stack is where it comes from.

Balanced is not fastest

Balancing rise and fall is not the same as minimizing delay. For an inverter driving an identical inverter with PMOS width $P$ (NMOS = 1), the fall delay is proportional to $P + 1$ and the rise delay to $(P + 1)\mu/P$. Their average is minimized at $P = \sqrt{\mu}$, not $P = \mu$.⁷ The wider PMOS speeds its own edge but loads the previous stage with more capacitance. That is one reason production cells often use a P/N ratio below the mobility ratio. The switching threshold barely cares: $V_{\mathrm{M}}$ depends on $\sqrt{k_{\mathrm{p}}/k_{\mathrm{n}}}$, so even a 10× change in $W_{\mathrm{p}}/W_{\mathrm{n}}$ moves it by well under $V_{\mathrm{DD}}/2$.⁵ A deliberately unbalanced skewed gate moves $V_{\mathrm{M}}$ toward one rail to speed one edge, and pays with a smaller noise margin on the other side.⁴

What stacks cost

• Resistance and internal capacitance. Upsizing a stack restores its resistance but adds diffusion capacitance at every internal node, and the Elmore delay of the stack charges those nodes through the devices below them. For a NAND3 driving $h$ identical gates, summing the RC terms of Harris’s NAND3 example gives a falling delay of $(12 + 5h)RC$ (the slide prints $11 + 5h$) versus $(9 + 5h)RC$ rising: the parasitic term is larger on the stacked side.⁴
• Body effect. Every device above the bottom of a stack has its source above the body while switching, which raises its threshold and lowers its drive.⁸
• Input capacitance. Logical effort grows linearly with $n$, which slows the gates that drive this one.⁶

Together these make delay grow faster than linearly in fan-in, so libraries cap NAND and NOR at about four inputs (SKY130 HD stops at nand4/nor4; the ASAP7 library goes to a weak NAND5 and NOR5).¹⁸¹⁹ Wider functions become trees, and the choice between “many simple stages” and “fewer high-fan-in stages” is a delay-versus-area decision made per path.⁷ The cell-level view of these decisions, drive strengths and characterized delays, is in From devices to a cell library.

Gates are generated from a series/parallel pull-down tree; the pull-up is its computed dual, and widths (×) come from series depth with $\mu = 2$, so the readouts give each input’s logical effort and the gate’s parasitic delay. Check NAND2 (4/3, 2), NOR2 (5/3, 2) and AOI21 (2 and 5/3, 7/3). On the inverter, the $W_{\mathrm{p}}/W_{\mathrm{n}}$ slider skews the square-law VTC ($V_{\mathrm{Tn}} = |V_{\mathrm{Tp}}| = 0.5\,\mathrm{V}$, $\lambda = 0.1\,\mathrm{V}^{-1}$, $V_{\mathrm{DD}} = 1.8\,\mathrm{V}$). Sweep it from 0.25 to 8, a 32× strength range, and note how little $V_{\mathrm{M}}$ moves while one noise margin grows at the other’s expense.

SKY130 Idsat at 7/0.15 µm: NMOS / PMOS / PMOS-hvt

3.51 / 1.35 / 1.00 mA

SKY130 inv_1 Wp/Wn

1.0 / 0.65 = 1.54

ASAP7 INVx1 fins (n / p)

3 / 3

65 nm example: static vs dynamic power

0.86 W vs 6.1 W

Device strengths in an open kit

SKY130’s device tables (typical corner, $W/L = 7/0.15\,\mu\mathrm{m}$) give the NMOS $V_{\mathrm{T}} \approx 0.645\,\mathrm{V}$ and $I_{\mathrm{dsat}} = 3.512\,\mathrm{mA}$; the standard PMOS $V_{\mathrm{T}} \approx -0.781\,\mathrm{V}$ and 1.347 mA; the high-$V_{\mathrm{T}}$ PMOS $V_{\mathrm{T}} \approx -0.888\,\mathrm{V}$ and 1.003 mA.¹⁰ The effective N/P drive ratio is 2.6 with the standard PMOS and 3.5 with the HVT one. The same page lists a fanout-of-1 inverter stage delay of 31.8 ps (nominal) for the standard NMOS/PMOS pair and 38 ps with the HVT PMOS: the slower pull-up is the price of lower PMOS leakage.¹⁰

How the cells are actually sized

The library does not follow the textbook. inv_1 pairs a 0.65 µm NMOS with a 1.0 µm HVT PMOS, a width ratio of 1.54 against a drive ratio of about 3.5.¹¹¹⁰ By the RC model its pull-up is roughly half as strong as its pull-down, so $V_{\mathrm{M}}$ sits below $V_{\mathrm{DD}}/2$ and rising edges are slower than falling ones. Since $\sqrt{3.5} \approx 1.9$, a ratio of 1.54 is in the range the least-average-delay argument favors over full balancing.⁷ Stacks are not upsized either: nand2_1 uses two series 0.65 µm NMOS, nor2_1 two series 1.0 µm PMOS, and nand4_1 four series 0.65 µm NMOS.¹²¹⁴¹⁵ At drive strength 1 the library minimizes area and input capacitance and lets characterization capture the weaker stacked edge. The same function also comes in larger drive strengths (nand2_2, nand2_4, nand2_8) for paths that need them.¹³

The FinFET ASAP7 library makes different choices, in whole fins. Its INVx1 uses 3 fins for both NMOS and PMOS (P/N = 1). NAND2x1 doubles the series NMOS to 6 fins against 3-fin PMOS, and NOR2x1 doubles the series PMOS to 6 fins against 3-fin NMOS: textbook stack compensation. NAND5xp2 stacks five 3-fin NMOS under 2-fin PMOS.¹⁹

.SUBCKT INVx1_ASAP7_75t_R A VDD VSS Y
MM0 Y A VSS VSS nmos_rvt w=81.0n l=20n nfin=3
MM1 Y A VDD VDD pmos_rvt w=81.0n l=20n nfin=3
.ENDS

.SUBCKT NAND2x1_ASAP7_75t_R A B VDD VSS Y
MM3 net16 A VSS VSS nmos_rvt w=162.00n l=20n nfin=6
MM2 Y B net16 VSS nmos_rvt w=162.00n l=20n nfin=6
MM1 Y B VDD VDD pmos_rvt w=81.0n l=20n nfin=3
MM0 Y A VDD VDD pmos_rvt w=81.0n l=20n nfin=3
.ENDS

Static power is not zero

Harris’s worked example of a 1-billion-transistor chip in a 1.0 V, 65 nm process estimates 6.1 W of switching power at 1 GHz and 859 mW of static power: 584 mA of subthreshold leakage (assuming high-$V_{\mathrm{T}}$ devices in all memory and 95% of logic) plus 275 mA of gate leakage.⁹ “Near-zero static current” is a statement about the circuit topology; the devices still leak, and the next chapter covers how much.

Static CMOS against the alternatives

• Ratioed logic (NMOS with a resistive or always-on PMOS load) uses $n + 1$ transistors and presents less input capacitance, but $V_{\mathrm{OL}}$ depends on the pull-down/load ratio and a DC current flows whenever the output is low. With a resistor load, noise margin and speed are in direct tension.³⁹
• Pass-transistor and transmission-gate logic save devices in multiplexers and XORs but pass levels without restoring them, so chains need buffering. An NMOS-only pass device also degrades the 1 by $V_{\mathrm{Tn}}$.⁴
• Static complementary CMOS pays $2n$ devices, the PMOS input load and inverting-only stages for rail-to-rail restoring outputs, no static current and robustness to sizing. That robustness is why it is the default for standard-cell logic.

Sizing and topology trade-offs

• P/N ratio. Balanced ($P = \mu$) gives $V_{\mathrm{M}} = V_{\mathrm{DD}}/2$ and equal edges; $P = \sqrt{\mu}$ gives less average delay and input capacitance; skewing favors one edge. Libraries choose per cell and per drive strength, as the SKY130 numbers show.⁷
• NAND vs NOR. With $\mu > 1$, a NOR’s PMOS stack makes it costlier than a NAND of the same fan-in ($g = 5/3$ vs $4/3$ at $n = 2$, 3 vs 2 at $n = 4$). Logic is restructured toward NANDs and AOIs where possible.⁶ The size of the penalty depends on $\mu$, which differs between processes; ASAP7’s 1:1 inverter shows a kit whose designers chose equal PMOS and NMOS fin counts.¹⁹
• Input ordering in stacks. The parasitic delay of a stacked gate depends on which input switches last. For a NAND2 falling edge, Harris’s estimate is $2\tau$ if the input nearest the output (the “inner” input) arrives last, and $2.33\tau$ if the input nearest the rail does, because then the internal node still has to be discharged. The rule: connect the latest-arriving signal to the inner input.⁷
• Leakage depends on the input vector. Series off devices leak about 10× less than a single off device (the stack effect), so a gate’s leakage depends on which inputs are 0. Sleep modes can park inputs in their lowest-leakage state.⁹

Failure modes

• Floating inputs put an inverter in region C, both devices on, with continuous current and an output that amplifies any noise on the input. Tie cells and input pull resistors exist for this.
• Bus contention (two tristate drivers enabled at once) creates the crowbar state between gates rather than within one: a DC path, heating and an undefined level.²
• Margin erosion. Supply droop at the driver, ground bounce at the receiver and crosstalk stack up against the same $\mathrm{NM}$. At low $V_{\mathrm{DD}}$ the margins themselves shrink.⁵
• Short-circuit power stays under about 10% of dynamic power only while input and output slews are comparable.⁹ A weak driver on a long wire breaks that assumption at the receiver, which is one reason flows enforce max-transition limits.

Solving for the switching threshold

At $V_{\mathrm{M}}$ both devices are saturated and carry the same current. In the long-channel square law, with $k_{\mathrm{n}} = \mu_{\mathrm{n}} C_{\mathrm{ox}} W_{\mathrm{n}}/L_{\mathrm{n}}$ and $k_{\mathrm{p}}$ likewise:³

Taking square roots and solving:

• With $r = 1$ and $V_{\mathrm{Tn}} = |V_{\mathrm{Tp}}|$, $V_{\mathrm{M}} = V_{\mathrm{DD}}/2$. Since $\mu_{\mathrm{n}} \approx 2\mu_{\mathrm{p}}$, that needs $W_{\mathrm{p}} \approx 2W_{\mathrm{n}}$.³
• As $k_{\mathrm{n}} \gg k_{\mathrm{p}}$, $V_{\mathrm{M}} \to V_{\mathrm{Tn}}$; as $k_{\mathrm{p}} \gg k_{\mathrm{n}}$, $V_{\mathrm{M}} \to V_{\mathrm{DD}} - |V_{\mathrm{Tp}}|$.³
• The square root compresses sizing changes. With the simulator’s values ($V_{\mathrm{DD}} = 1.8\,\mathrm{V}$, $V_{\mathrm{T}} = 0.5\,\mathrm{V}$), $r = 0.5$ gives $V_{\mathrm{M}} = 0.77\,\mathrm{V}$ and $r = 2$ gives 1.03 V: a 16× change in $k_{\mathrm{p}}/k_{\mathrm{n}}$ moves $V_{\mathrm{M}}$ by 0.27 V. That insensitivity is why $V_{\mathrm{M}}$ is robust to process variation in the P/N ratio.⁵

Velocity-saturated devices change the exponent: current is closer to linear than quadratic in overdrive. Redo the algebra with $I \propto k V_{\mathrm{ov}}$ and $r$ becomes $k_{\mathrm{p}}/k_{\mathrm{n}}$ instead of its square root, so the same imbalance moves $V_{\mathrm{M}}$ further from $V_{\mathrm{DD}}/2$. The shape of the argument is the same. The model behind that is in The I-V curve.

Gain and two ways to estimate noise margins

Linearizing around $V_{\mathrm{M}}$ gives the small-signal gain $A_{\mathrm{v}} = -(g_{\mathrm{mn}} + g_{\mathrm{mp}})(r_{\mathrm{on}} \parallel r_{\mathrm{op}})$.³ A quick piecewise-linear estimate replaces the curve with three straight segments: flat at $V_{\mathrm{DD}}$, a line of slope $A_{\mathrm{v}}$ through $(V_{\mathrm{M}}, V_{\mathrm{M}})$, flat at 0. Then:³

For the simulator’s balanced inverter, $g_{\mathrm{m}} = k V_{\mathrm{ov}} \approx 40\,\mu\mathrm{A/V}$ per device at $V_{\mathrm{ov}} = 0.4\,\mathrm{V}$ and $I \approx 8.7\,\mu\mathrm{A}$, so $r_{\mathrm{o}} \approx 1/(\lambda I) \approx 1.1\,\mathrm{M}\Omega$ and $|A_{\mathrm{v}}| \approx 80\,\mu\mathrm{A/V} \times 0.57\,\mathrm{M}\Omega \approx 46$ (the sim’s numerical derivative, which includes the $(1 + \lambda V_{\mathrm{ds}})$ factor in the current, reports about 54). The piecewise estimate then gives $\mathrm{NM}_{\mathrm{L}} \approx \mathrm{NM}_{\mathrm{H}} \approx 0.88\,\mathrm{V}$. The unity-gain definition gives 0.68 V for the same curve. The piecewise version assumes the steep segment runs straight to the rails, ignoring the rounded knees of regions B and D, so it is optimistic. Use it for intuition about gain and the unity-gain numbers for budgets.

Sizing stacks and logical effort

Logical effort expresses a gate’s delay in units of $\tau$ (the delay of an ideal inverter driving an identical one) as $d = gh + p$, where $h = C_{\mathrm{out}}/C_{\mathrm{in}}$ is the electrical effort.⁶ The procedure behind the $g$ values, which the simulator follows:

1. Size every device so the worst-case path through each network matches a unit inverter (NMOS 1, PMOS $\mu$). A device on a path of $k$ series devices gets width $k$ (or $k\mu$). For nested series-parallel networks, $k$ is the longest series path through that device.
2. $g = (\text{sum of widths that input drives})/(1 + \mu)$ for each input. For an $n$-input NAND with $\mu = 2$: $(n + 2)/3$. For NOR: $(2n + 1)/3$.⁶
3. $p \approx (\text{diffusion width on the output node})/(1 + \mu)$, counting the devices that touch the output. That gives $p = n$ for an $n$-input NAND or NOR, and $p = 1$ for the inverter.⁶ For AOI21 it gives $g_{\mathrm{A}} = 2$, $g_{\mathrm{B}} = 5/3$ and $p = 7/3$.

The FO4 delay, $d = 1 \cdot 4 + 1 = 5$, is the common yardstick; Harris quotes about 15 ps in a 65 nm process.⁶ Logical effort counts only output diffusion in $p$, so it understates the cost of tall stacks. Elmore delay adds the internal nodes. In the NAND3 example (NMOS width 3, PMOS 2, driving $h$ identical NAND3s), summing $R_i \times C_{\mathrm{downstream}}$ along the stack gives a falling delay of $(12 + 5h)RC$ against $(9 + 5h)RC$ rising.⁴ For an $n$-high stack whose internal nodes each carry capacitance proportional to $n$, the internal-node terms sum to something proportional to $n(n - 1)/2$. That quadratic growth is the formal version of “keep fan-in at four or below.”

The best P/N ratio

For an inverter with NMOS width 1 and PMOS width $P$ driving an identical inverter, the unit-RC delays are $t_{\mathrm{pdf}} \propto P + 1$ and $t_{\mathrm{pdr}} \propto (P + 1)\mu/P$. Minimize the average:⁷

With $\mu = 2$, $P = 1.41$ gives $t_{\mathrm{pd}} \approx 2.91$ against 3.00 for $P = 2$: about 3% faster on average and 20% less input capacitance, at the cost of unequal edges. Harris tabulates the same optimization for NAND2 and NOR2.⁷ Libraries land between the two answers, and real data (such as SKY130’s 1.54 ratio with a 3.5× drive gap) reflects the area, leakage and layout limits the RC model ignores.¹¹

Leakage and the stack effect

Subthreshold current falls by about a decade for every 100 mV of threshold: Harris’s 65 nm example gives $I_{\mathrm{off}} \approx 100\,\mathrm{nA}/\mu\mathrm{m}$ at $V_{\mathrm{T}} = 0.3\,\mathrm{V}$, 10 nA/µm at 0.4 V and 1 nA/µm at 0.5 V.⁹ In a two-high stack of off NMOS, the node between them settles at a small $V_x > 0$. The upper device then sees $V_{\mathrm{gs}} = -V_x$, a body-effect $V_{\mathrm{T}}$ increase and a smaller $V_{\mathrm{ds}}$ (less drain-induced barrier lowering), and its current drops about 10×; three-high stacks cut it further.⁹ Leakage-aware flows exploit this through high-$V_{\mathrm{T}}$ cells, stacking and input-vector control in sleep. All of them trade against delay, the subject of Speed and power.