Power planning

You know that a design becomes a netlist of logic gates and is then laid out. Every one of those gates, the standard cells, needs a supply connection (VDD) and a ground connection (VSS), and power planning builds the wiring that provides them: the on-chip part of the power delivery network. The wiring is a mesh of metal on the chip’s ten or so stacked wiring layers. Its quality is measured by how much voltage is lost on the way to each cell, the IR drop (current $I$ times resistance $R$), and by whether any wire carries enough current to wear out over the product’s life, the electromigration limit.

The useful way to think about the stage is as a budget in three currencies. The first is routing tracks: each metal layer has evenly spaced lanes that wires must run along, and every lane given to power is taken from signal and clock wires. The second is chip area, for capacitor cells that steady the supply and switch cells that turn blocks off. The third is voltage margin, how far the supply may sag before logic becomes too slow to meet the clock. A denser grid has lower resistance and makes the drop and wear-out limits easier to meet, but it uses more tracks.⁶ At the most advanced manufacturing nodes power wiring takes at least 20% of routing resources, while the power rails inside every cell limit how small the cells can be made.⁵

The grid is not built once. A first version is built from predefined patterns (templates) at floorplan time, using estimates of each block’s power and the positions of the package connections. It is refined after placement, when the real current and routing-congestion maps are known.⁶ Final verification on the routed layout is part of Signoff. Two things complicate the picture. Blocks that can be switched off, or that run at their own voltage, each need their own grid, switches and boundary cells. And at the newest manufacturing nodes the whole grid can move to the back of the silicon wafer. The sections below take each piece in turn: the budget for voltage sag, where the worst point sits and why, how wire wear-out is checked, switched domains, the package, and finally the solvers that compute all of it.

Routing resources taken by power interconnect at advanced nodes

≥20%

IR drop reduction from backside power with buried rails (imec and Arm simulation)

7×

Source: Horiguchi and Beyne at imec.⁵

The inputs are the floorplan, the technology’s layer rules and the cell outlines (in the DEF and LEF file formats), each cell’s power data (Liberty), switching activity from simulation (SAIF or VCD files) once it exists, the power intent (UPF), and the foundry’s current limits. The outputs are the wiring, written to DEF as special nets, plus any switch and capacitor cells, and analysis reports. Two of those inputs decide whether an early voltage-drop number means anything, and both are easy to get wrong.

Where the current is. The analysis needs to know how much current each point of the grid draws. Before placement no cell has a position yet, so the current is estimated per block and spread evenly over the block’s area. After placement, OpenROAD’s analyzer computes each cell’s power itself and lets you override individual cells by hand.³ A uniform spread hides the hot spots that placement will create, so early numbers are a sanity check, not a verdict.

Where the supply comes from. Power enters the chip through solder bumps on its face (flip-chip packaging) or pads around its edge. The analysis has to model those entry points as voltage sources, and OpenROAD’s analyzer offers three choices: treat every point on the top metal layer as a perfect supply, model an array of bumps, or model straps on an imaginary layer above the top. Its bump model defaults to a 140 µm spacing, can leave out bumps to account for the ones that carry signals instead of power, and can add an external resistance to stand in for the package.³ The “every point is a perfect supply” option is the optimistic one: it ignores the voltage lost traveling sideways from a bump, and the points between bumps are often where the worst drop is. Record which model a reported number used.

Splitting the droop budget

Start from the number the timing analysis assumes. Each cell’s delay was characterized at some supply voltage, and the chip only meets its clock if the voltage each cell really sees is not much lower. The total allowed sag, often held under about 10% of $V_{\mathrm{DD}}$, has two main sources: IR drop through the resistance of the grid, and $L\,di/dt$ noise, the voltage lost when current changes quickly through the inductance of the package and bumps.¹ They depend on different things:

• Static drop is set by grid resistance and average current. You fix it with wider or denser straps and more via cuts.
• Dynamic drop is set by how fast current changes, how much charge-storing capacitance (decap) sits close enough to help, and the package. You fix it with decap placement, package design, and limiting how fast activity ramps up.

Treat each as a line item, and check that their sum matches the voltage the timing libraries assume. Dynamic drop also depends on what the chip is assumed to be doing. Vector-based analysis replays switching activity recorded from simulating real workloads (a VCD waveform file). It is accurate for the time windows it covers, but covering a large chip needs a huge number of patterns, and good patterns arrive late in the project. Vectorless analysis assumes the activity instead. It is faster and available earlier, but harder to make accurate.⁷

Where the worst node is

Picture the grid as a network of resistors with supply connections at fixed points. The voltage a cell sees is the supply minus the drop along its path from the supply points, so the worst point is wherever the paths are longest and carry the most current. In a wire-bond chip, power enters only around the edge, so the center of the die has the longest path. In a flip-chip design the bumps form a regular array, and the points farthest from any bump sit at the center of the square formed by four neighboring bumps.²² Not every bump site carries power, since some carry signals, so the power bumps are thinned out and sit farther apart than the bump spacing alone suggests.³ Zoom in and the same logic repeats. Between two straps, current has to travel sideways along the thin, resistive rails on the lowest layer to reach the nearest via stack, so the low points sit midway between straps. The simulation below shows exactly this.

Via stacks and track cost

To get from a strap on M7 down to a rail on M1, current passes through a via on every layer in between. Each intermediate layer needs a small metal landing pad for the vias above and below it, and a large via array grows those pads into patches that block the signal lanes next to them. OpenROAD’s grid generator lets you cap the rows and columns of each via array, snap intermediate layers onto the routing lanes, and keep pass-through layers at minimum width, so the stack uses a single row of cuts across that layer and doesn’t spread into neighboring lanes.² A second lever is to vary the pitch by region. Template-based grid synthesis picks a pitch for each region from a small library of patterns designed to join cleanly at their edges. On average it frees thousands of routing tracks in crowded regions compared with one uniform grid, while still meeting the IR and electromigration limits.⁶

Checking wire wear-out

Electromigration checks follow a recipe. Compute the current in every wire segment and via, from the same resistor-network solution that gives the voltage drop. Divide by the cross-section to get current density. Compare it with a limit derived from Black’s equation, an empirical formula for how a wire’s expected life falls as current density and temperature rise (written out in Under the hood). Then clear any short segment that passes the Blech test: in a short enough wire, the mechanical stress that builds up pushes atoms back as hard as the current pushes them forward, and the wire never fails.⁸ Power grids are redundant, with many parallel paths. A failed segment raises the voltage drop elsewhere without immediately breaking the chip, but it pushes more current, and so a higher chance of failure, into the paths that remain.⁸

There is a convenient link between the two checks. The stress that builds up along a segment is proportional to its current density times its length, and that product is proportional to the segment’s voltage drop. So optimizing a grid for IR drop also tends to improve its resistance to electromigration.⁸ OpenROAD’s analyzer can write out the current in every grid segment (its -enable_em option), which is enough to spot undersized via arrays early.³

Decap placement

When current changes very fast, a capacitor far away is little help: its charge has to travel through the grid, and the grid’s inductance limits how quickly it can arrive. At high frequencies the supply of charge is highly localized, and the useful amount of decap is set mainly by the grid’s inductance.¹² Decap far from a hotspot does little for the first dip, even if the chip-wide total looks generous. Flows therefore reserve room for decap near clusters of busy logic, or insert it where the analysis shows the worst drop.³ How much to add is limited by the area and leakage it costs.¹¹ Decap also adds to the chip’s total capacitance, which forms a resonant circuit with the package’s inductance (see Package, board and the backside below).¹⁰

Switch sizing and sequencing

A power switch is a resistor in series with everything in its block while it is on, so the voltage lost across the switches comes out of the block’s drop budget. When it is off, it still leaks a little. Switches must be sized for the block’s switching current: more total width lowers the on-state drop, but adds leakage and area.¹⁴ More drive current also shortens wake-up but raises the surge.¹⁵ A wake-up sequence divides the switches into groups and turns the groups on one by one, in an order chosen to keep the surge under a limit while keeping wake-up short.¹⁵ In UPF a switch can have several control inputs, one per stage, and acknowledge outputs that report back to the power controller when each stage is on.¹⁶

A small always-on power controller runs the sequence, and the order follows from what each cell protects against. Isolation must be active whenever the block’s outputs might be unknown, so it goes on before power-down and comes off last, after the switches have acknowledged and the state is back. Retention registers save their state before the supply goes and restore it once the supply is stable again. Each of those control signals must exist in the design, and UPF names them in set_isolation_control and set_retention_control.¹⁶

The always-on supply inside switched blocks

Some cells inside a switched block must stay powered: isolation cells placed there, the backup latches of retention registers, and buffers that carry always-on signals across the block. They need the unswitched supply inside the block, which OpenROAD’s grid generator models as a secondary power net of the voltage domain.² That net needs its own straps or pin connections, sized for everything that stays awake. It is easy to undersize because those cells are few, yet the retention cells all switch together during save and restore.

Power states drive analysis

A power state table lists the legal combinations of supply states, for example run, sleep and hibernate.¹⁶ Each row is a separate scenario for drop and electromigration analysis. The worst static drop is often in the all-on, highest-voltage state, but the worst dynamic event can be a wake-up: one block’s rush current hitting a grid it shares with a neighbor running at full speed.¹⁴¹⁵

The impedance profile

Chip, package and board form one electrical network, and its impedance (resistance generalized to changing currents) varies with frequency. Board components set it at low frequencies, the package in the middle, and on-chip elements at high frequencies.¹¹ Two consequences follow. First, the target impedance, $Z = \Delta V / \Delta I$ (the allowed ripple divided by the largest current step), has to be met across the whole range, not at one frequency.¹³ Second, the on-chip capacitance and the package inductance together form a resonant circuit, like a mass on a spring, with a main resonance at about 100–200 MHz in one published analysis of a 90 nm processor. At that frequency die and package act as one, and decap anywhere on the die helps; above it, decap helps only locally.¹⁰

Harris’s Pentium 4 example shows the result: an impedance spike near 100 MHz caused by package inductance. When current jumps in a step, the supply dips three times, and each dip is answered by a different stage: the first by on-chip capacitance, the second by the package’s capacitors, the third by the board’s.¹ The chip team controls the first dip through decap and grid design, and that is where power planning meets package design. Because the resonance frequency depends on the die capacitance (see Under the hood), every added nanofarad of decap moves the resonance and changes its peak, so an accurate analysis of the on-chip grid needs a package model.¹⁰ For the static (DC) analysis, OpenROAD’s external-resistance setting is the simplest way to put the package in the loop.³

Backside delivery in practice

Backside power delivery moves the grid under the transistors. imec’s approach combines buried power rails, which replace the cell rails on the lowest metal layer with metal lines about 30 nm wide at about 100 nm pitch sunk below the transistors, with nano-TSVs at 200 nm pitch that reach them from the back without taking any standard-cell area.⁵ Taking the power wiring off the front relieves signal congestion: PowerVia test cores packed some regions up to 95% full.¹⁹ The planning problem changes with it. The backside stack has its own layers, widths and via rules; front-side straps and their track cost largely disappear; and cell libraries change, because the rails move below the transistors.⁵ Heat removal needed new design rules, and debugging needed new methods, because the transistors are sandwiched between two wiring stacks.¹⁹

Behind the map, the simulation writes one current-balance equation per grid point (the $G\mathbf{v} = \mathbf{i}$ system explained in Under the hood) and solves it by successive over-relaxation, a simple method that sweeps the grid over and over, nudging each point’s voltage toward the value its neighbors imply, until nothing changes. It reports how many sweeps that took, along with the worst drop and the share of tracks the straps use. With the hotspot on, compare two fixes: a narrower pitch everywhere, or wider straps. Both cost tracks; note which buys more millivolts per percent of tracks spent. Then look at where the worst drop sits relative to the straps and the edge connections, and think about how a real flow would respond: denser straps only over the hotspot, decap next to it, or a different bump arrangement. Watch the sweep count too. This kind of simple relaxation slows down as grids grow, which is why real tools use the solvers in Under the hood.²⁰

Here are three files from one illustrative design: a chip block containing a DSP (a digital signal processor, a unit full of multiply-and-add hardware) that can be switched off when idle. First, the summary report from static IR-drop and electromigration (EM) analysis after placement, run twice: before and after a local fix. Read it top to bottom: the setup, the result, where the drop accumulates layer by layer, and what changed in the second run.

==== Static IR / EM summary (illustrative) ====
Net: VDD   Nominal 0.750 V   Budget 5.0% = 37.5 mV   Sources: bumps, 140 um pitch
Total current 1.84 A   Grid: M1 rails, M4/M7/M9/M10 straps

RUN 1 (uniform grid)
  Worst drop          41.2 mV  (5.5%)   u_dsp/u_mac_array  (612.4, 488.0)
  Instances > budget  3,418
  Drop by layer at worst node:
    bump + M10/M9     6.1 mV
    M7                7.9 mV
    M4                9.6 mV
    M1 rails + vias  17.6 mV
  EM: 2 via arrays V1-V3 over Javg limit (1.21x, 1.08x) at u_mac_array

RUN 2 (M4 pitch 20 -> 10 over u_dsp only, V1-V3 arrays 2x3 -> 3x3, decap added)
  Worst drop          29.8 mV  (4.0%)   u_dsp/u_mac_array  (618.0, 492.6)
  Instances > budget  0
  EM: 0 segments over limit
  M4 track usage      4.8% core-wide, 9.6% inside u_dsp region
  Congestion delta    +2.1% overflow in u_dsp region (global route estimate)

Second, the power intent for the DSP, written in UPF (IEEE 1801). It declares two power domains, the always-on top level (PD_TOP) and the switchable DSP (PD_DSP), and the supply nets that feed them. The DSP switches off in sleep, keeps some state in retention registers, and holds its outputs at 0 through isolation cells while it is off. Its power switch has two control inputs, so it can turn on in two stages, and a power state table lists which supply combinations are legal.¹⁶

# dsp_power.upf  (illustrative IEEE 1801 power intent)
create_power_domain PD_TOP
create_power_domain PD_DSP -elements {u_dsp}

create_supply_port VDD
create_supply_port VSS
create_supply_net  VDD -domain PD_TOP
create_supply_net  VSS -domain PD_TOP
create_supply_net  VSS -domain PD_DSP -reuse
create_supply_net  VDD_DSP_SW -domain PD_DSP
connect_supply_net VDD -ports VDD
connect_supply_net VSS -ports VSS
set_domain_supply_net PD_TOP -primary_power_net VDD -primary_ground_net VSS
set_domain_supply_net PD_DSP -primary_power_net VDD_DSP_SW -primary_ground_net VSS

create_power_switch SW_DSP -domain PD_DSP \
    -input_supply_port  {vin VDD} \
    -output_supply_port {vout VDD_DSP_SW} \
    -control_port {stage1_en u_pmu/dsp_stage1_en} \
    -control_port {stage2_en u_pmu/dsp_stage2_en} \
    -ack_port {stage1_ack u_pmu/dsp_stage1_ack {stage1_en}} \
    -ack_port {stage2_ack u_pmu/dsp_stage2_ack {stage2_en}} \
    -on_state  {full_on vin {stage1_en & stage2_en}} \
    -off_state {full_off {!stage1_en & !stage2_en}}

set_isolation ISO_DSP -domain PD_DSP -applies_to outputs -clamp_value 0 \
    -isolation_power_net VDD -isolation_ground_net VSS
set_isolation_control ISO_DSP -domain PD_DSP \
    -isolation_signal u_pmu/dsp_iso -isolation_sense high -location parent

set_retention RET_DSP -domain PD_DSP \
    -retention_power_net VDD -retention_ground_net VSS
set_retention_control RET_DSP -domain PD_DSP \
    -save_signal {u_pmu/dsp_ret posedge} -restore_signal {u_pmu/dsp_ret negedge}

add_port_state VDD -state {ON 0.75}
add_port_state SW_DSP/vout -state {ON 0.75} -state {OFF off}
add_port_state VSS -state {GND 0.0}
create_pst pst_main -supplies {VDD VDD_DSP_SW VSS}
add_pst_state RUN   -pst pst_main -state {ON ON  GND}
add_pst_state SLEEP -pst pst_main -state {ON OFF GND}

Third, the physical side of the same intent, in OpenROAD’s grid generator (pdngen): a region of the chip whose cell rails carry the switched supply, with header switch cells wherever those rails meet the always-on mesh above, chained so they turn on one after another.²

# pdn_dsp.tcl  (illustrative, OpenROAD pdngen syntax; units in um)
define_power_switch_cell -name HDRSW_X4 -control SLEEP -acknowledge SLEEP_ACK \
    -power_switchable VDDV -power VDD -ground VSS

set_voltage_domain -name DSP -region dsp_region -power VDD -ground VSS \
    -switched_power VDD_DSP_SW

define_pdn_grid -name dsp_grid -voltage_domains {DSP} \
    -power_switch_cell HDRSW_X4 -power_control u_pmu/dsp_stage1_en \
    -power_control_network DAISY
add_pdn_stripe  -grid dsp_grid -layer M1 -followpins
add_pdn_stripe  -grid dsp_grid -layer M4 -width 0.48 -pitch 10.0 -offset 1.0
add_pdn_connect -grid dsp_grid -layers {M1 M4}
add_pdn_connect -grid dsp_grid -layers {M4 M7}

pdngen

• Decap in the wrong place. Plenty of total decap on paper, but far from the hotspot, does little for the first and fastest dip, because at high frequency charge only travels a short distance.¹²
• Vectorless results taken as truth, or ignored. Vectorless analysis assumes switching activity rather than measuring it. Taken literally, its pessimism drives overdesign; dismissed, it hides real risk. Calibrate it against waveform-based runs on known stress patterns.⁷
• Wake-up never analyzed. One block’s rush current at wake-up is a dynamic drop event for its neighbors. Simulate it with the real switch chain and schedule.¹⁵
• An undersized always-on supply. The unswitched supply inside a switchable block feeds few cells and gets few straps, then dips when all the retention registers save or restore at once.
• Via arrays as the weak link. Wide straps pass the electromigration check while the via arrays that feed them fail. Check via current as well as wire current.⁸
• Late grid changes. The grid is meant to be set from templates at floorplan time and refined incrementally after placement.⁶ Changing strap pitch wholesale after placement moves the blocked tracks under cells that are already placed, so earlier routing estimates no longer hold. Keep later changes local.
• Decap budgets without a package model. The die’s capacitance and the package’s inductance resonate together, so sizing decap without a package model misjudges that resonance.¹⁰

The grid as a circuit

Every analysis tool starts by turning the layout into a circuit. Each wire segment and via becomes a resistor (plus capacitance for time-varying analysis); the network is linear, doesn’t change over time, and contains no sources of its own. Each bump or pad becomes an ideal voltage source, and each cell or block becomes a current that varies over time. Writing Kirchhoff’s current law (current in equals current out) at every node gives a matrix equation:

Here $\mathbf{x}$ holds the node voltages, $G$ the conductances ($1/\text{resistance}$) between nodes, $C$ the capacitances, and $\mathbf{u}(t)$ the sources and cell currents.²⁰ Kozhaya and colleagues leave out on-chip inductance as too small to matter, and Pant and colleagues found the on-die grid behaves as an RC network except for very fast, very local effects.¹⁰ Qian and colleagues argue that in the top few metal layers inductance can no longer be ignored, and include it in their solver.²² The challenge is scale: for a modern microprocessor the network can easily include millions of nodes and tens of millions of elements.²⁰

Static analysis: $G\mathbf{v} = \mathbf{i}$

For static (DC) analysis, drop the capacitance. At a node $x$ with neighbors $i$, Kirchhoff’s law says

the currents flowing in from the neighbors, each conductance $g_i$ times a voltage difference, add up to the current $I_x$ the node’s cells draw. Writing that for every node gives one big linear system, $G\mathbf{v} = \mathbf{i}$. The matrix $G$ is sparse (each node touches only a few neighbors) and symmetric positive definite, a property that the fast solvers below rely on.²²

A two-node example makes it concrete. A rail is fed from $V_{\mathrm{DD}} = 0.75\,\mathrm{V}$ through two segments of 2 Ω each (conductance 0.5 S), and each of the two nodes draws 1 mA. The equations are

Solving gives $v_1 = 0.746\,\mathrm{V}$ and $v_2 = 0.744\,\mathrm{V}$. The far node sees 6 mV of drop: 4 mV in the first segment, which carries both nodes’ 2 mA, and 2 mV in the second. A real grid is the same thing with millions of rows, which is why the solver matters.

Direct solution: Cholesky factorization

The textbook way to solve $G\mathbf{v} = \mathbf{i}$ is to factor $G$ into a lower-triangular matrix times its transpose ($G = LL^{\top}$, Cholesky factorization) and then solve two easy triangular systems. Because $G$ is symmetric positive definite, Cholesky needs roughly half the computation of general LU factorization and no row swapping (pivoting) for stability. Reordering the nodes first, with heuristics such as minimum degree or nested dissection, limits fill-in, the new nonzero entries that factoring creates.²¹ For time-varying analysis with a fixed time step $h$, the matrix to factor is $G + C/h$ at every step, and it never changes, so one factorization serves the whole simulation and each step costs only the two triangular solves. Kozhaya and colleagues found 100 steps per clock cycle sufficient for digital power grids.²⁰ The weakness is size: solve time grows faster than linearly with the matrix, which pushes the largest grids toward iterative methods.²⁰

Preconditioned conjugate gradient

Conjugate gradient is an iterative method for symmetric positive definite systems. It improves a guess step by step using only matrix–vector products, and the number of steps it needs depends on how badly conditioned the matrix is. A preconditioner is a cheap approximation of the matrix’s inverse that makes the problem better conditioned. A common choice is an incomplete Cholesky factorization, which limits fill-in by level or drops entries below a size threshold. Power-grid matrices are often badly conditioned, so this preconditioning is critical.²¹ The threshold is a dial: keeping more fill-in gives a more effective preconditioner but costs more to build and apply.²¹

Multigrid

Simple iterations such as Jacobi, Gauss–Seidel and the over-relaxation used in the simulation above update each node from its neighbors. Think of the error in the current guess as a pattern across the grid. These methods quickly flatten jagged, node-to-node error (high-frequency error) but remove smooth, slowly varying error very slowly, so they need more sweeps as the grid gets finer. Multigrid alternates the two things that work: a few relaxation sweeps to smooth the error, then a correction computed on a coarser grid, where smooth error looks jagged and is cheap to remove. A system of $N$ equations is then solved in $O(N)$ work, proportional to its size.²⁰ Kozhaya, Nassif and Najm adapted the idea to irregular power grids: reduce the grid to a coarser one, solve that, and map the solution back. Their method was fast for both static and time-varying analysis, with a worst-case error of about 16% in the voltage drop on their test designs, a trade that suits early planning better than final checks.²⁰

Random walks

Rearranged, the node equation says

a node’s voltage is a weighted average of its neighbors’, minus a term for the current it draws. Qian, Nassif and Sapatnekar read this as a game. A walker starts at node $x$ and at each step moves to neighbor $i$ with probability $g_i / \sum_j g_j$, paying a “motel” cost of $I_x / \sum_j g_j$ at every node it passes. Voltage sources are “homes”: reaching one ends the walk with a payout of $V_{\mathrm{DD}}$. The expected money left at the end equals $V_x$. Averaging $M$ walks estimates it, with an error whose variance falls as $1/M$, so accuracy is a dial you trade against runtime.²²

The method is local: one node’s voltage needs only walks that start there, which suits quick what-if checks on part of a grid, and nodes already solved can become new homes that shorten later walks. It struggles where homes are rare, as in wire-bond grids with supply pads only on the edges, where a walk from the center wanders for a very long time. It also struggles where an upper layer’s wires are much more resistive than the vias beneath it, so walkers keep wandering in the well-connected lower layers instead of climbing to the sources. Hierarchical variants address both. The paper reports a 71K-node flip-chip grid solved in 4.16 s, and time-varying analysis with inductance of a 642K-node grid at 2.1 s per time step.²²

Dynamic analysis with and without vectors

Vector-based dynamic analysis takes cell currents from simulating the design on real input patterns (recorded in VCD files), so it is only as complete as those patterns.⁷ Kouroussis and Najm framed the alternative by analogy with static timing analysis, which checks timing without any input patterns. They verify the grid by giving each current source an upper bound (a local constraint) and each group of sources, such as a block or the whole chip, a combined upper bound from its known power (a global constraint). Linear programming then finds the worst drop over every combination of currents that satisfies those bounds. With local constraints alone, every source can peak at once, and the result is very pessimistic; the global constraints bring it back toward reality.²³ Practical vectorless analysis works from assumed switching activity instead. It is fast and early, but harder to make accurate than vector-based analysis.⁷

Black’s equation and the Blech limit

Electromigration limits come from Black’s equation:

The time to failure $t_{50}$ falls as a power $n$ of the current density $j$, and exponentially as the temperature $T$ rises ($E_{\mathrm{a}}$ is an activation energy, $k$ Boltzmann’s constant, and $A$ a fitted constant). Black derived $n = 2$; later work puts $n$ between 1 and 2. $A$ and the statistical spread of failure times come from accelerated tests on single wires at high current and temperature. Reliability engineers turn a failure-rate target and a product lifetime into a minimum $t_{50}$ for each wire, and so into a maximum allowed current density.⁸ A worked example: with $n = 2$, 25% more current density leaves $1.25^{-2} = 0.64$ of the original life. Blech found that short wires resist electromigration. If $j$ times the wire length $L$ stays below a technology constant, $(jL)_{\mathrm{crit}}$, the stress that builds up pushes atoms back as hard as the electron flow pushes them forward, and the wire is “immortal”.⁸⁹

Target impedance and resonance

In the frequency domain the requirement is $|Z(f)| \le Z_{\mathrm{target}} = \Delta V / \Delta I$ at every frequency $f$.¹³ One of the hardest points to meet is the resonance of the die’s capacitance with the package’s inductance.¹⁰ An inductance $L$ and a capacitance $C$ resonate at

With illustrative values of 30 pH of effective package inductance and 100 nF of die capacitance, $f \approx 92\,\mathrm{MHz}$, close to the 100 MHz spike in Harris’s Pentium 4 example.¹ Adding decap raises $C$ and so lowers $f$ and changes the peak, and the resistance in the loop (its damping) sets how high the peak rises. That is why chip and package teams size decap and package inductance together.