Guide 1 of 4 · 8 chapters + 2 optional

Transistors

Every chip is built from transistors: tiny switches with no moving parts, flipped on and off by electricity. This guide shows how they work, how they’re made and how they team up to do math and remember things.

Start with the MOSFET as a voltage-controlled switch. Build logic gates and memory cells from it, see why speed, power and size trade off against each other, and finish at the cell library that chip designers work from.

From the MOSFET’s current-voltage behavior to short-channel effects, FinFETs and gate-all-around devices, fabrication, SRAM stability and cell characterization, with two open process kits (SKY130 and ASAP7) for real numbers.

The Expert level assumes you know a transistor is a switch controlled by a voltage, and not much more.

  1. The device · how the switch works

    01The switch
    A transistor is a tiny switch with no moving parts. Electricity on one wire decides whether electricity can flow through the other two. A phone chip holds billions of them.
    A MOSFET has a gate, a source and a drain. A voltage on the gate pulls charge into a thin channel underneath it, which connects source to drain. NMOS transistors turn on when the gate is high; PMOS transistors turn on when it’s low.
    Model the MOSFET as a voltage-controlled switch with a threshold voltage, an on-resistance and a gate capacitance. Those three numbers explain most of what digital designers care about, and the later chapters refine each one.
    Full chapter
  2. 02CMOS logic
    Join two switches so that when one is on, the other is off. Now the output is always the opposite of the input: on becomes off, and off becomes on. Every logic gate on a chip is built from pairs like this.
    An inverter stacks a PMOS pull-up above an NMOS pull-down. NAND and NOR gates extend the idea with switches in series and in parallel. Because one side is always off, a CMOS gate draws almost no current while it holds a value.
    Complementary pull-up and pull-down networks, the voltage transfer curve and noise margins, why CMOS gates are naturally inverting, sizing PMOS against NMOS for balanced edges, and why stacking limits a gate’s inputs.
    Full chapter
  3. 03The I-V curve
    A transistor isn’t only on or off. In between, it lets some electricity through, like a tap opened partway. This chapter maps how far open it is.
    Drain current depends on the gate voltage and the drain voltage. Below the threshold the device is nearly off. Above it, current grows with gate voltage and then levels off as drain voltage rises. A simple model, the square law, captures the shape.
    Cutoff, linear and saturation regions; the long-channel square law and where it breaks down: velocity saturation, channel-length modulation and subthreshold conduction. How each one shapes drive current and output resistance.
    Full chapter
  4. 04Speed and power
    Every time a switch flips, it uses a little energy and takes a little time. Giving the chip a stronger push of electricity makes it faster, but it runs hotter and drains the battery sooner.
    Gate delay comes from charging capacitance through a transistor’s on-resistance. Switching power grows with capacitance, the square of the voltage and the clock frequency, and leakage flows even when nothing switches. Lower voltage saves power but slows every gate.
    RC and alpha-power delay models, CV²f switching power, subthreshold and gate leakage, multi-threshold cell libraries, and why supply voltage stopped falling in step with transistor size: the end of Dennard scaling.
    Full chapter

  5. On the chip · making and using it

    05Shrinking
    For decades, transistors shrank every couple of years. At tiny sizes they started to leak, so their shape changed: from flat, to a thin fin, to a path the switch’s control wraps all the way around.
    As channels got shorter the gate lost control, and transistors leaked even when off. FinFETs wrap the gate around three sides of a fin. Gate-all-around transistors wrap it around stacked sheets. Newer ideas stack NMOS on PMOS and move the power wiring under the transistors.
    Short-channel effects (DIBL, degraded subthreshold slope), the planar → FinFET → gate-all-around nanosheet transition, stacked CFETs, backside power delivery, and why node names stopped describing a physical dimension. FinFET-era numbers come from the open ASAP7 predictive kit.
    Full chapter
  6. 06Making them
    Chips are made on thin discs of silicon, layer by layer. Light shines through a stencil to print patterns far too small to see. Each disc goes through hundreds of steps before it’s done.
    Lithography prints each layer’s pattern; deposition, etching, implantation and polishing build it. The transistors are made first, then the stack of metal wiring above them. Yield measures how many chips on a wafer come out working.
    Immersion and EUV lithography, multi-patterning, front-end, middle and back-end of line, process control, and yield models that connect defect density and die area to cost.
    Full chapter
  7. 07Memory cells
    Chips remember ones and zeros in tiny cells made of transistors. Some memory is fast but takes lots of room. Other memory packs in more but is slower.
    An SRAM cell holds a bit in two inverters wired in a loop, six transistors in all. A DRAM cell stores the bit as charge on a capacitor and has to be refreshed. Flash traps charge so the bit survives with the power off.
    6T SRAM read and write stability, static noise margin and the butterfly curve, DRAM sensing and refresh, charge trapping in NAND flash, and how these trade-offs set the memory hierarchy that AI chips depend on.
    Full chapter
  8. 08From devices to a cell library
    Designers don’t place transistors one at a time. They pick from a catalog of ready-made pieces, like building bricks, each with a known speed and power use.
    A standard cell is a pre-drawn layout of a gate, such as an inverter, a NAND or a flip-flop. Every cell has the same height so they line up in rows. Each cell’s delay and power are measured and stored in Liberty files that the design tools read.
    Cell architecture (track height, power rails, pin access), the layout of an inverter and a flip-flop in an open process kit, NLDM timing tables and interpolation, and how a library connects transistor physics to the spec-to-GDS flow.
    Full chapter

  9. Optional deep dive

    +Bands, doping and the p-n junction
    Why does silicon act like a switch at all? This optional chapter looks inside the material. A pinch of other elements lets silicon carry electricity only where and when we want.
    Electrons in silicon sit in energy bands with a gap between them. Doping adds free electrons (n-type) or holes (p-type). Where n-type and p-type regions meet, a junction forms that lets current flow one way, and the MOSFET is built on that idea.
    Band diagrams, the Fermi level, doping and carrier concentration, the p-n junction under bias, and the MOS capacitor from accumulation to inversion: the physics behind threshold voltage.
    OptionalFull chapter
  10. +Fins and nanosheets
    Chip switches changed shape: from flat, to a thin fin, to a stack of ribbons the control wraps all the way around. This optional chapter shows what each shape is good at, how it is made, and why companies give the same idea different names.
    Planar transistors, FinFETs and gate-all-around nanosheets are all MOSFETs. Each step wraps more gate around a thinner channel, which cuts leakage, allows a lower supply voltage and packs more current into the same space. Intel’s Tri-Gate and RibbonFET, Samsung’s MBCFET and TSMC’s nanosheet are brand names for these same types.
    Effective width per footprint and fin quantization, gate control and supply voltage, capacitance, variability and self-heating, the Si/SiGe superlattice, inner spacers and channel release, forksheets, and a map from each company’s transistor names to the generic device types.
    OptionalFull chapter