The switch

You know a MOSFET is a voltage-controlled switch. For digital design that model needs three numbers to become useful: a threshold voltage $V_{\mathrm{T}}$ that says where the switch flips, an on-resistance $R_{\mathrm{on}}$ that says how much current it passes when closed, and a gate capacitance $C_{\mathrm{g}}$ that says how much charge it costs to flip. Add the subthreshold current that still flows when it is “open” and you have the first-order model behind delay, power and leakage estimates.⁶

This chapter puts real numbers on those parameters from the open SKY130 process kit, derives where each comes from, and shows where the switch model stops being accurate. Later chapters refine each piece: the full I-V curve in The I-V curve, delay and leakage power in Speed and power, and short-channel effects in Shrinking. The band physics of inversion lives in the optional physics chapter.

The structure: n+ source and drain diffusions in a p-type body (for NMOS), separated by a channel of length $L$ and width $W$, under a gate electrode on a thin dielectric. The gate–oxide–body stack is a MOS capacitor with $C_{\mathrm{ox}} = \varepsilon_{\mathrm{ox}}/t_{\mathrm{ox}}$ per unit area.⁴ Source and drain are symmetric; the source is whichever terminal is at the lower potential (for NMOS), so $V_{\mathrm{DS}} \ge 0$ by construction.⁴

The terminal voltages that matter are all referenced to the source:

• $V_{\mathrm{GS}}$ sets the channel charge. Below $V_{\mathrm{T}}$ the surface is depleted but not inverted; above it, the inversion charge per area is about $C_{\mathrm{ox}}(V_{\mathrm{GS}} - V_{\mathrm{T}})$.
• $V_{\mathrm{DS}}$ drives carriers along the channel. For a switch, what matters is the current at $|V_{\mathrm{DS}}| = V_{\mathrm{DD}}$ (the drive current, $I_{\mathrm{on}}$) and the slope near $V_{\mathrm{DS}} = 0$ (the channel resistance).
• $V_{\mathrm{SB}}$ shifts $V_{\mathrm{T}}$ through the body effect. It is zero for a transistor whose source is tied to its body, but not for the upper devices in a series stack.⁵

In SKY130 the 1.8 V NMOS sits in a p-well, optionally inside a deep n-well that isolates it from the substrate; the PMOS sits in an n-well tied to $V_{\mathrm{DD}}$.⁸² The gate is a polysilicon line 0.18 µm thick¹⁰ over an oxide whose electrical thickness in the typical NMOS model is 4.148 nm (4.23 nm for PMOS).¹¹¹² The models are binned down to a minimum drawn length of 0.15 µm.¹¹

For a switch-level model, treat $V_{\mathrm{T}}$ as the knee between two exponentially different regimes:

• Above threshold, the long-channel (Shockley) model gives $I_{\mathrm{DS}} = \frac{\beta}{2}(V_{\mathrm{GS}} - V_{\mathrm{T}})^2$ in saturation, with $\beta = \mu C_{\mathrm{ox}} W/L$.⁴ Short devices are partly velocity-saturated, so the exponent falls toward 1 (about 1.3 at 65 nm in the alpha-power fit).⁵
• Below threshold, current is diffusion-limited and exponential: $I_{\mathrm{DS}} \propto 10^{(V_{\mathrm{GS}} - V_{\mathrm{T}})/S}$, where the subthreshold swing $S = n\,(kT/q)\ln 10$.⁵ The thermal limit ($n = 1$) is about 60 mV/decade at room temperature¹⁴, and Harris’s rule of thumb, with $n \approx 1.3\text{–}1.7$, is about 100 mV/decade.⁵

$V_{\mathrm{T}}$ is not one number per process. SKY130’s typical-corner NMOS threshold is 0.538 V on a 7/8 µm device and 0.645 V on a 7/0.15 µm device; the PMOS goes the other way, −1.050 V long and −0.781 V short.⁸ It also moves with:

• Source-to-body bias (the body effect), drain voltage (drain-induced barrier lowering, DIBL) and channel length (short-channel effects).⁵
• Temperature: $V_{\mathrm{T}}$ falls as temperature rises, so $I_{\mathrm{off}}$ rises while $I_{\mathrm{on}}$ drops because mobility falls too.⁵
• Implants: the same process offers low- and high-$V_{\mathrm{T}}$ flavors (SKY130’s low-$V_{\mathrm{T}}$ NMOS is 0.434 V long-channel) for the speed-versus-leakage trade.⁸

PMOS is NMOS with every doping and sign inverted: p+ diffusions in an n-well tied to $V_{\mathrm{DD}}$, a hole channel, $V_{\mathrm{GS}}$ and $V_{\mathrm{T}}$ negative.² Hole mobility is typically 2–3× lower than electron mobility, which is why the textbook RC model gives a unit PMOS twice the resistance of a unit NMOS.⁴⁶ SKY130’s typical numbers for $W/L = 7/0.15\,\mu\mathrm{m}$: $I_{\mathrm{dsat}} = 3.512\,\mathrm{mA}$ (NMOS) and 1.347 mA (PMOS), a ratio of 2.6.⁸

The pass-transistor asymmetry falls out of the threshold: an NMOS with its gate at $V_{\mathrm{DD}}$ stops conducting when its source reaches $V_{\mathrm{DD}} - V_{\mathrm{T}}$, and the body effect makes that $V_{\mathrm{T}}$ larger than nominal because the source is now well above the body. A PMOS likewise stalls at $|V_{\mathrm{Tp}}|$.⁶⁵ Static CMOS sidesteps both by giving every output a PMOS pull-up network to $V_{\mathrm{DD}}$ and an NMOS pull-down network to ground. Where a switch must pass both levels, a transmission gate puts an NMOS and a PMOS in parallel.³ See CMOS logic for the networks and their sizing.

The Expert view adds a channel-width slider, the drain current on a log plot, and three model outputs: an effective on-resistance ($0.75\,V_{\mathrm{DD}}/I_{\mathrm{D}}$), the intrinsic gate capacitance $C_{\mathrm{ox}} W L$, and the off-state leakage. The device model is calibrated to SKY130’s typical 1.8 V numbers ($V_{\mathrm{T}}$, $I_{\mathrm{dsat}}$, $t_{\mathrm{ox}}$, $L = 0.15\,\mu\mathrm{m}$). Try:

• Read the subthreshold slope off the plot: how many millivolts per decade?
• Sweep $W$ from 0.5 to 7 µm and watch $R_{\mathrm{on}}$, $C_{\mathrm{g}}$ and their product. Which one stays put, and why?
• Compare the on/off ratio and $R_{\mathrm{on}} C_{\mathrm{g}}$ for NMOS and PMOS.

The model has no DIBL, velocity saturation or gate leakage, so its off-current is lower than silicon’s and its above-threshold shape is only approximate. Use it for trends.

Harris’s RC model replaces each transistor with an ideal switch, an effective resistance and its capacitances: a unit NMOS is $R$ with gate, source and drain capacitance $C$ each; a unit PMOS is $2R$; $k$ times the width gives $R/k$ and $kC$.⁶ The effective resistance is not the small-signal channel resistance; it is averaged over the switching transient so that $t_{\mathrm{pd}} \approx RC$.⁶

For SKY130, using $R_{\mathrm{eff}} \approx 0.75\,V_{\mathrm{DD}}/I_{\mathrm{on}}$ (derived in Under the hood) with the typical $I_{\mathrm{dsat}}$ values⁸:

That is below Harris’s 6 kΩ·µm for a 0.6 µm process, consistent with resistance improving at shorter channel lengths.⁶

Intrinsic gate capacitance from the SKY130 NMOS model’s 4.148 nm oxide: $C_{\mathrm{ox}} = 3.9\,\varepsilon_0/t_{\mathrm{ox}} \approx 8.3\,\mathrm{fF}/\mu\mathrm{m}^2$, so $C_{\mathrm{ox}} W L \approx 1.25\,\mathrm{fF}$ per µm of width at $L = 0.15\,\mu\mathrm{m}$.¹¹ Overlap and fringe capacitance add to that, and the diffusion capacitance on source and drain is comparable to $C_{\mathrm{g}}$ for contacted diffusion.⁴ Harris’s planning numbers are 2 fF/µm in 0.6 µm, falling toward 1 fF/µm in nanometer processes.⁶

Two consequences to keep in mind. First, $R_{\mathrm{eff}} \propto 1/W$ and $C_{\mathrm{g}} \propto W$, so a transistor driving an identical transistor has a width-independent time constant ($2.7\,\mathrm{k}\Omega{\cdot}\mu\mathrm{m} \times 1.25\,\mathrm{fF}/\mu\mathrm{m} \approx 3.4\,\mathrm{ps}$ for SKY130 NMOS, intrinsic only). Upsizing pays off only against a fixed external load such as a wire or a large fanout, which is the logic behind logical effort and buffer chains. Second, the SKY130 fanout-of-1 inverter delay listed in the documentation is 31.8 ps nominal⁸, roughly ten times that intrinsic figure. A real inverter also charges the PMOS gate, both drain junctions and local wiring, and its PMOS is the weaker device, so the intrinsic number is a floor, not a prediction.

Front end of line (FEOL) forms wells, gates and source/drain diffusions; back end of line (BEOL) adds the contacts, the metal layers and the vias between them.²¹⁵ Every transistor terminal reaches the outside world through that stack, so its resistance and capacitance are part of the switch’s real load.

SKY130’s stack, from the process rules¹⁰⁹:

For the device model this means gate and diffusion capacitance are only part of what a driver sees: the wires through this stack add their own resistance and capacitance, which is why extracted parasitics feed signoff timing. Lower layers are thin and dense for short connections; upper layers are thicker for long routes and power. Advanced nodes change parts of this picture, covered in Shrinking.

Points worth noting in this data:

• The short NMOS has a higher $V_{\mathrm{T}}$ than the long one, while the short PMOS has a lower $|V_{\mathrm{T}}|$. Threshold versus length is process-specific, which is why libraries characterize each device size rather than assume one $V_{\mathrm{T}}$.
• The corner spread is large: $I_{\mathrm{dsat}}$ for the NMOS runs from 3.078 mA (SS) to 3.945 mA (FF), and the documented inverter delay spans 24.7 ps (min) to 44.1 ps (max).⁸ Timing signoff has to cover that range.

For leakage, a textbook reference point: Harris’s 65 nm example has an off-current of 100 nA/µm at $V_{\mathrm{T}} = 0.3\,\mathrm{V}$, 10 nA/µm at 0.4 V and 1 nA/µm at 0.5 V, one decade per 100 mV of threshold.⁷

$V_{\mathrm{T}}$ and $V_{\mathrm{DD}}$

Drive scales with $(V_{\mathrm{DD}} - V_{\mathrm{T}})^{\alpha}$, $1 < \alpha < 2$⁵, while off-current scales as $10^{-V_{\mathrm{T}}/S}$. With $S$ above the 60 mV/decade limit and near 100 mV/decade in Harris’s numbers¹⁴⁵, each 100 mV cut in $V_{\mathrm{T}}$ costs roughly a decade of leakage. That floor on $V_{\mathrm{T}}$ is why $V_{\mathrm{DD}}$ stopped scaling (the story of Speed and power), and why multi-$V_{\mathrm{T}}$ libraries and leakage recovery after timing closure are standard.

Sizing

Because $RC$ of a device driving its own kind is width-independent, sizing is a question of matching drive to external load, not of making everything big. Oversizing raises input capacitance, leakage and area, and pushes the problem one stage back. PMOS/NMOS width ratios trade rise/fall balance against input capacitance.⁶

Failure modes of the switch abstraction

• Body effect and stacks. $V_{\mathrm{SB}} > 0$ in series stacks raises $V_{\mathrm{T}}$ of upper devices, cutting their drive and limiting practical stack height.⁵
• DIBL. High $V_{\mathrm{DS}}$ lowers $V_{\mathrm{T}}$ in short devices, so off-current depends on drain voltage.⁵ Conversely, two off transistors in series leak about ten times less than one (the stack effect), because the node between them rises and gives the upper one a negative $V_{\mathrm{GS}}$.⁷
• Temperature. $I_{\mathrm{off}}$ rises with temperature while $I_{\mathrm{on}}$ falls, so leakage is worst at the hot corner and drive is often worst there too.⁵
• Gate leakage. Tunneling through thin $\mathrm{SiO_2}$ approaches subthreshold leakage at 65 nm and below in some processes; high-k dielectrics are the fix.⁷
• Degraded levels. Single-polarity pass devices leave outputs $V_{\mathrm{T}}$ (plus body effect) short of the rail, so the next stage’s PMOS or NMOS is never fully off, and it leaks.⁶

The three-number switch model, derived step by step from the long-channel equations, and the smooth model the simulation uses.

1. Channel charge and the linear region

Treat gate, oxide and channel as a parallel-plate capacitor. Above threshold, the mobile charge in the channel is⁴

where the $V_{\mathrm{DS}}/2$ term is the average channel potential. Carriers move with velocity $v = \mu E = \mu V_{\mathrm{DS}}/L$, so they take $t = L^2/(\mu V_{\mathrm{DS}})$ to cross. Current is charge over transit time:

For small $V_{\mathrm{DS}}$ this is a resistor: $R_{\mathrm{ch}} = 1/[\beta(V_{\mathrm{GS}} - V_{\mathrm{T}})]$. It falls as the gate overdrive rises and scales as $L/W$. Once $V_{\mathrm{DS}} > V_{\mathrm{GS}} - V_{\mathrm{T}}$ the channel pinches off at the drain and the current saturates at $\frac{\beta}{2}(V_{\mathrm{GS}} - V_{\mathrm{T}})^2$.⁴

2. From channel resistance to effective resistance

Delay is measured to the 50% point, so the useful resistance is the one that reproduces the discharge time of a load $C$ from $V_{\mathrm{DD}}$ to $V_{\mathrm{DD}}/2$. Harris defines it as $R$ averaged across the switching event.⁶ A quick estimate, with its assumption stated:

1. Assume the pull-down stays in saturation, carrying roughly $I_{\mathrm{on}}$, while its $V_{\mathrm{DS}}$ falls from $V_{\mathrm{DD}}$ to $V_{\mathrm{DD}}/2$. This is a simplifying assumption; it is closer to the truth the lower the device’s saturation voltage.
2. Its instantaneous resistance $V_{\mathrm{DS}}/I_{\mathrm{on}}$ then goes linearly from $V_{\mathrm{DD}}/I_{\mathrm{on}}$ to $(V_{\mathrm{DD}}/2)/I_{\mathrm{on}}$.
3. The average is $R_{\mathrm{eff}} \approx \tfrac{3}{4}\, V_{\mathrm{DD}}/I_{\mathrm{on}}$.

For SKY130 NMOS, $0.75 \times 1.8\,\mathrm{V} / 3.512\,\mathrm{mA} \approx 384\,\Omega$ at $W = 7\,\mu\mathrm{m}$, or 2.7 kΩ·µm.⁸

3. Gate capacitance from oxide thickness

1. $C_{\mathrm{ox}} = \varepsilon_{\mathrm{ox}}/t_{\mathrm{ox}} = \frac{3.9 \times 8.854 \times 10^{-12}\,\mathrm{F/m}}{4.148 \times 10^{-9}\,\mathrm{m}} \approx 8.3 \times 10^{-3}\,\mathrm{F/m^2}$, which is 8.3 fF/µm².⁴¹¹
2. Multiply by the gate area: at $L = 0.15\,\mu\mathrm{m}$, $C_{\mathrm{ox}} L \approx 1.25\,\mathrm{fF}$ per µm of width.
3. Add overlap (gate over source/drain extensions) and fringe fields, which are not in this number, to reach the 1–2 fF/µm rule of thumb.⁶

The $t_{\mathrm{ox}}$ used here is the SPICE model’s fitted oxide-thickness parameter (toxe), so treat the result as a model estimate rather than a measurement.

4. Subthreshold current and the off state

Below threshold the current is exponential in gate voltage:

with $v_{\mathrm{T}} = kT/q \approx 25.9\,\mathrm{mV}$ at 300 K. The factor $n = 1 + C_{\mathrm{d}}/C_{\mathrm{ox}}$ reflects how much of the gate voltage is lost across the depletion capacitance instead of moving the surface potential; $n = 1$ gives the 60 mV/decade limit.¹⁴ With $n = 1.6$, $S \approx 95\,\mathrm{mV/decade}$, and an NMOS with $V_{\mathrm{T}} = 0.645\,\mathrm{V}$ at $V_{\mathrm{GS}} = 0$ sits about $0.645/0.095 \approx 6.8$ decades below its threshold current. DIBL lowers the effective $V_{\mathrm{T}}$ at high $V_{\mathrm{DS}}$ and raises the current, so real off-currents exceed this estimate.⁵

5. One smooth model for the simulation

The sim needs a single expression that is exponential below $V_{\mathrm{T}}$ and square-law above it, with no discontinuity at the knee. It uses a softplus interpolation:

• Far above $V_{\mathrm{T}}$, $\ln(1 + e^x) \to x$, so $I_{\mathrm{D}} \to K (W/L)(|V_{\mathrm{GS}}| - |V_{\mathrm{T}}|)^2$: the square law with $K = \beta/2$ per square.
• Far below, $\ln(1 + e^x) \to e^x$, so $I_{\mathrm{D}} \propto \exp\!\big((|V_{\mathrm{GS}}| - |V_{\mathrm{T}}|)/(n\, v_{\mathrm{T}})\big)$: the subthreshold exponential with $S = n\, v_{\mathrm{T}} \ln 10$.
• $K$ is calibrated per device type so that $W/L = 7/0.15\,\mu\mathrm{m}$ at $|V_{\mathrm{GS}}| = 1.8\,\mathrm{V}$ reproduces SKY130’s typical $I_{\mathrm{dsat}}$ (3.512 mA NMOS, 1.347 mA PMOS), with $V_{\mathrm{T}} = 0.645\,\mathrm{V}$ and −0.781 V.⁸

What it leaves out, in order of importance for a switch: velocity saturation (the $\alpha$-power exponent near 1.3 rather than 2 in short channels), DIBL, the body effect, mobility degradation at high gate field, and gate and junction leakage.⁵ The I-V curve chapter adds $V_{\mathrm{DS}}$ dependence and those corrections.

6. The body effect

With the source above the body, the gate must support extra depletion charge before inversion, raising the threshold:⁵

where $\phi_{\mathrm{s}}$ is the surface potential at threshold (set by body doping) and $\gamma$ is the body-effect coefficient (larger for thicker oxide and heavier doping). For small $V_{\mathrm{SB}}$ it is often linearized as $V_{\mathrm{T}} \approx V_{\mathrm{T0}} + k V_{\mathrm{SB}}$.⁵ The derivation of $\phi_{\mathrm{s}}$ and $\gamma$ from the MOS capacitor belongs to the physics chapter.