From devices to a cell library

A standard-cell library is the contract between device physics and the digital flow. Below it, everything is transistors, models and layout rules. Above it, synthesis, placement, routing and static timing analysis (STA) see only abstractions: a Boolean function, an outline with pins, and tables of delay, slew, power and timing checks.¹ None of those tools simulates a transistor; whatever the earlier chapters showed about drive current, capacitance and threshold voltage reaches them only through the library.

Concretely, each cell is a bundle of views: GDS (the layout), LEF (the abstract for place-and-route), a SPICE or CDL netlist (for characterization and for layout-versus-schematic, or LVS, checking that the drawn layout matches the circuit), Verilog (for simulation), and one Liberty model per process/voltage/temperature (PVT) corner. The open SKY130 high-density library, sky130_fd_sc_hd, publishes all of them per cell and per drive strength, including Liberty data at sixteen corners.⁴¹³

This chapter walks through that contract in the order it’s built:

1. The cell architecture (height in tracks, rails, sites, pin access).
2. The layout of an inverter and a flip-flop in SKY130, with ASAP7 for a FinFET comparison.
3. Characterization in SPICE.
4. How a non-linear delay model (NLDM) table is read, including interpolation and extrapolation.
5. How synthesis and placement consume the result.

The numbers come straight from the open library files, so you can check every one.

Cell architecture

A standard cell is a fixed-height, site-aligned layout with its supply rails on the top and bottom edges.¹ The textbook template is:

• PMOS in an n-well along the VDD rail and NMOS along the GND rail.
• Horizontal diffusion strips with vertical polysilicon gates crossing them.
• Every gate designed to abut its neighbors without breaking a design rule.

That fixed template is what makes automated placement possible.¹⁷ In sky130_fd_sc_hd the unit site (unithd) is 0.46 × 2.72 µm, and the library is quoted as 9 met1 tracks tall.³

The inverter’s LEF shows how the rails work:⁸

• VPWR and VGND are 0.48 µm met1 rectangles centered on the cell’s top and bottom edges.
• Half of each rail belongs to the cell and half to the row above or below.
• Both pins carry SHAPE ABUTMENT, telling the router that abutment connects them.

Flows create rows from the site definition (OpenROAD’s initialize_floorplan -site) and alternate their orientation between N and FS (flipped), so each rail is shared by two rows.²³

Track height is the main density knob

Height in tracks sets three things: how wide the devices can be, how much wiring fits inside the cell, and how many access points each pin has. SKY130 shows the trade within one process:³

• hd (9 tracks, 2.72 µm) targets a routed density of 160 kGates/mm² or better and, compared with the 11-track ls library, lower dynamic power with comparable timing and leakage.
• hdll uses the same height and claims 5–10× lower leakage than hd.
• ls, ms and hs are 11 tracks (3.33 µm), graded by speed. hs cells are drop-in compatible with ms cells of the same function and drive strength.

Advanced nodes push height down to 7.5 or 6 tracks. The open ASAP7 FinFET kit ships both a 7.5-track and a 6-track library.¹⁵ At those heights each pin has very few legal access points, and pin access becomes a placement constraint, not just a routing detail.

Pins and local interconnect

In SKY130 hd, signal pins sit on li1, a local-interconnect layer below met1. In the inverter, A is a single 0.33 × 0.24 µm rectangle and Y is a set of three rectangles.⁸ The router reaches them through a via from met1. Libraries keep pins on the lowest layers so that upper layers stay free for routing over the cells.

Families, footprints and swaps

Each function comes in a family of drive strengths. In SKY130 that’s inv_1 through inv_16.⁵ Liberty groups them with a shared cell_footprint ("sky130_fd_sc_hd__inv" for every inverter), and the library header sets in_place_swap_mode : match_footprint.¹⁴ Optimizers use this to resize a cell without disturbing its neighbors. OpenROAD’s resizer has a -match_cell_footprint option for exactly that.²⁵

Taps, endcaps and fill

The textbook template puts well and substrate contacts in every gate.¹⁷ SKY130 hd provides a separate substrate-and-well tap cell, tapvpwrvgnd, with no logic pins.⁷ The flow places it in a checkerboard at a fixed distance (OpenROAD’s tapcell -distance), along with endcaps at row ends, before any logic is placed.²⁴ The spacing exists because taps keep the well and substrate resistance low enough that the parasitic p-n-p-n structure (a thyristor) formed by the wells and diffusions can’t switch on and latch up; SkyWater’s documentation lists latch-up protection among the tap grid’s jobs.²⁶³

inv_1 from netlist to abstract

The netlist is two devices:⁹

• sky130_fd_pr__nfet_01v8, $W = 0.65\,\mu\mathrm{m}$, $L = 0.15\,\mu\mathrm{m}$.
• sky130_fd_pr__pfet_01v8_hvt, $W = 1.0\,\mu\mathrm{m}$, $L = 0.15\,\mu\mathrm{m}$. This is a high-threshold PMOS: the library mixes threshold flavors inside the cell, not only between libraries.

The cell is 3 sites (1.38 µm) wide. A is a single li1 rectangle and Y is three. The LEF also records ANTENNAGATEAREA on A and ANTENNADIFFAREA on Y for the router’s antenna checks, which stop long wires from collecting enough charge during manufacturing to damage a thin gate.⁸ Here is the abstract, trimmed:

MACRO sky130_fd_sc_hd__inv_1
  CLASS CORE ;
  SIZE  1.380000 BY  2.720000 ;
  SYMMETRY X Y R90 ;
  SITE unithd ;
  PIN A
    ANTENNAGATEAREA  0.247500 ;
    DIRECTION INPUT ;
    PORT
      LAYER li1 ;
        RECT 0.320000 1.075000 0.650000 1.315000 ;
    END
  END A
  PIN VGND
    DIRECTION INOUT ;
    SHAPE ABUTMENT ;
    USE GROUND ;
    PORT
      LAYER met1 ;
        RECT 0.000000 -0.240000 1.380000 0.240000 ;
    END
  END VGND
END sky130_fd_sc_hd__inv_1

dfxtp_1: a master-slave flop in 16 sites

dfxtp_1 is a positive-edge D flip-flop built from two latches.¹⁷⁶ Its netlist has 24 transistors. CLK feeds an inverter that drives a second inverter, producing the complementary internal clocks, and the output stage drives Q with its own 0.65 µm NMOS and 1.0 µm PMOS, the same sizes as the inverter’s.¹¹ The cell is 7.36 µm (16 sites) wide, 5.3 inverter-widths, with CLK marked USE CLOCK in the LEF so clock-tree tools treat it as a sink.¹⁰

Its Liberty model holds more than delay tables. There are setup and hold constraint tables indexed by clock transition and data transition, and a minimum-pulse-width check on CLK. At the fastest edges (10 ps on both pins), the typical-corner values are:¹⁴

• Setup: 50.8 ps for a rising D and 103.3 ps for a falling D.
• Hold: −28.5 ps and −46.8 ps.

A negative hold means D may change slightly before the clock edge and still be captured correctly. The numbers move with slew: at a 1.5 ns clock edge and a fast D, setup for a rising D drops to −45 ps.

The same cells in ASAP7

ASAP7’s 7.5-track library uses a 0.054 × 0.270 µm site. INVx1 is 3 sites (0.162 µm) and DFFHQNx1 is 20 sites (1.08 µm).¹⁶ The comparison with SKY130:

• Inverter area: 3.75 µm² versus 0.044 µm², about 86 times smaller.
• Flip-flop area: 20.0 µm² versus 0.29 µm², about 69 times smaller.
• Site width: 0.46 µm versus 54 nm; row height: 2.72 µm versus 0.27 µm.

The flop shrank less than the inverter: area scaling is uneven across cell types.

Characterization is SPICE run at scale. The inputs are the cell’s extracted netlist (with layout parasitics), the foundry’s device models, and a template that fixes the measurement setup: the index grid, the thresholds, and the input driver.¹⁸¹⁹ The outputs, per corner, are:

• The cell’s function, recognized from the transistor network or declared.
• Every timing arc, with timing_sense (the inverter’s A→Y is negative_unate) and timing_type (combinational, rising_edge, setup_rising, hold_rising, min_pulse_width).
• cell_rise, cell_fall, rise_transition and fall_transition tables.
• Internal-power tables, state-dependent leakage, and pin capacitances (separately for rise and fall).

Open characterizers (LibreCell’s lctime, CharLib, libretto) do the same job in the open.¹⁸

Measurement conventions

The SKY130 hd header fixes the measurement setup:¹⁴

• Delay is measured from the input’s 50% crossing to the output’s 50% crossing (input_threshold_pct and output_threshold_pct are 50).
• Transition is measured from 20% to 80% of the swing, with slew_derate_from_library 1.0.
• The input stimulus is a linear ramp (driver_model : "ramp"). Its normalized_driver_waveform confirms the convention: the 10 ps index is a ramp that reaches full swing in 16.7 ps, because 20–80% is 0.6 of the swing.

Getting these conventions wrong when mixing libraries silently shifts every delay. Units are time_unit : "1ns" and capacitive_load_unit(1, "pf").

Grid design

Every SKY130 hd delay table uses del_1_7_7: input_net_transition on index_1 and total_output_net_capacitance on index_2.

• Transition axis: 10 ps to 1.5 ns in steps of about 2.3×.
• Load axis: per cell, from 0.5 fF up to the pin’s max_capacitance.

For inv_1 the last load index is 0.181284 pF, and the output’s max_capacitance is the same number.¹² The grid stops exactly at the design-rule limits, so a netlist that obeys max_transition and max_capacitance never needs to read past the top edge. Geometric spacing puts more points where the surface bends most, at small slews and loads. A rule of thumb from open characterization practice: choose the grid so that linear interpolation between points is good enough, and choose the bounds so that extrapolation is never needed.¹⁸

Constraint arcs

Setup and hold are found by bisection: move the data edge toward the clock until the output fails (or until clock-to-Q degrades by a set percentage; SKY130’s files record violation_delay_degrade_pct : "10"). Each point needs many simulations, which is why constraint tables are coarser, 3 × 3 in dfxtp_1.¹⁴

Corners and data volume

SKY130 hd publishes sixteen corners, from ff_n40C_1v95 to ss_100C_1v40, two of them with CCS noise data. The typical-corner Liberty file alone is about 12 MB for 428 cells.¹³¹⁴ Libraries offered in several threshold-voltage flavors multiply that again, which is why characterization is a compute-farm job and why a model update means re-characterizing everything.

An NLDM arc is four 2-D tables:

• cell_rise and cell_fall give delay as a function of input transition and output load.
• rise_transition and fall_transition give the output slew over the same grid.

For a negative-unate arc like the inverter’s, a rising input produces cell_fall, and STA picks the table that matches the output edge.¹²

The lookup

OpenSTA’s implementation is short enough to state in full.²⁰

1. Find $i$ such that $\texttt{index\_1}[i] \le s \le \texttt{index\_1}[i+1]$ by bisection, and $j$ the same way for load $c$. Clamp $i$ to $[0, n-2]$, so a point past the last index uses the last interval.
2. Compute $u = (s - s_i)/(s_{i+1} - s_i)$ and $v = (c - c_j)/(c_{j+1} - c_j)$.
3. Return the weighted sum of the four corners:
   $$\begin{aligned} &(1-u)(1-v)\,y_{00} + u(1-v)\,y_{10} \\ &\quad + uv\,y_{11} + (1-u)v\,y_{01} \end{aligned}$$

Interpolation is linear in the raw index values, even though the grid is spaced geometrically.

Worked example

inv_1 cell_rise, $s = 100\,\mathrm{ps}$, $c = 5\,\mathrm{fF}$:¹²

• Rows 53.13 and 122.47 ps give $u = 46.87/69.34 = 0.676$.
• Columns 3.565 and 9.521 fF give $v = 1.435/5.955 = 0.241$.
• The four entries are $y_{00} = 56.6$, $y_{01} = 90.3$, $y_{10} = 84.7$ and $y_{11} = 121.1\,\mathrm{ps}$.

weights: (1-u)(1-v) = 0.246   u(1-v) = 0.513
         (1-u)v     = 0.078   uv     = 0.163
delay  = 0.246*56.6 + 0.513*84.7 + 0.078*90.3 + 0.163*121.1
       = 13.9 + 43.5 + 7.0 + 19.7
       = 84.2 ps
slew   = same weights on rise_transition  ->  59.6 ps

What the surface looks like

• Along a row, delay is close to linear in load at large loads. The slope is an effective drive resistance: about 5.6 ps/fF (5.6 kΩ) for inv_1 rising, and 1.8 ps/fF for inv_4.¹⁴
• Down a column, slow inputs add delay because the cell spends longer partly on.
• Negative entries are real. inv_4’s cell_fall reaches −53.7 ps at a 1.5 ns input and 0.5 fF. A strong, lightly loaded inverter pulls its output through 50% before a slow input gets there. The same effect bends inv_1’s cell_fall back down in its last row at the lightest load (31.7 ps, below the 46.7 ps above it).
• Some tables are nearly flat. dfxtp_1’s CLK→Q rise_transition barely changes with clock slew (23.3–23.6 ps in every row at 0.5 fF), because Q is driven by an internal stage, not directly by CLK.

Extrapolation

Because the index is clamped and $u$ or $v$ is not, a point outside the grid gets a straight-line continuation of the edge interval. The open-source characterization literature warns that extrapolation can produce large errors depending on the grid bounds.¹⁸ In SKY130 hd the bounds are the design-rule limits, so the high side is also a max_transition or max_capacitance violation, which the flow repairs by buffering or upsizing rather than trusting the number.²⁵ The low side (below 10 ps or 0.5 fF) extrapolates over a short distance and is usually benign.

Each view feeds a different consumer, and a mismatch between views is a classic source of late surprises.

Three practical consequences follow. The dont_use list (cells kept out of synthesis) is a library-quality decision, not a design one. A library update must keep LEF, Liberty and GDS in step, or timing and layout describe different cells. And the corner set you load at synthesis decides what “meets timing” means long before signoff.

The lookup reproduces OpenSTA’s: bisection on each axis, index clamped to the edge interval, bilinear weights shown with their arithmetic. Things to check:

• Compare the load slope of inv_1 and inv_4 along the top row.
• Find inv_4 fall’s negative corner at 1.5 ns and 0.5 fF.
• Push load past max_capacitance and watch $v$ exceed 1 while the extrapolated delay keeps climbing linearly.
• Read the output transition readout for dfxtp_1 at different clock slews.

Corner spread

Interpolating inv_1 cell_rise at 50 ps and 5 fF in three corners gives:¹³⁴

• 51 ps at ff_n40C_1v95 (fast transistors, cold, high voltage).
• 63 ps at tt_025C_1v80 (typical).
• 88 ps at ss_100C_1v60 (slow transistors, hot, low voltage).

That’s a 1.7× spread for one gate. Note that the slow corner uses different index values (its load axis runs to 410 fF), so comparisons need interpolation, not entry-by-entry reading.

Drive strength in numbers

Along the 10 ps row, inv_1’s cell_rise slope between its 25 and 68 fF columns is 5.6 ps/fF. inv_4’s between 54 and 175 fF is 1.8 ps/fF, 3.1 times lower.¹⁴ The price:

• 3.9× the input capacitance (9.0 versus 2.3 fF).
• 1.7× the area (6.26 versus 3.75 µm²).

The area grows less than the drive partly because the smallest sizes don’t fill their footprint: inv_2 fits in the same 3.75 µm² as inv_1.¹⁴

• Track height. Fewer tracks buy density and lower capacitance at the cost of drive, internal routing and pin access points. SKY130 sells the trade as hd (9 tracks) versus hs (11).³ ASAP7 offers 7.5 and 6 tracks.¹⁵ Mixing heights in one block needs row planning, because the rails must line up.
• Library richness. Complex cells (AOI/OAI, muxes, multibit flops) let the mapper absorb logic levels, but each one adds characterization, layout and verification cost, and some are poor for pin access and end up on a dont_use list.
• Grid resolution. NLDM error is largest where the surface curves most, at small slews and loads and wherever a crossover such as the negative-delay region sits between grid points. Denser grids cut interpolation error and multiply simulation count.¹⁸
• Model fidelity. NLDM gives a delay and a ramp slew into a lumped capacitance. Resistive wires shield far-end capacitance, and real waveforms aren’t ramps, so advanced nodes add current-source models that store output current.¹⁸ The SKY130 hd release includes CCS noise data at two corners.¹³ The cost is larger files and slower analysis.
• Design-rule limits as guard rails. Because SKY130 ends its grid at max_transition and max_capacitance, those limits double as “no extrapolation” fences. A library whose grid ends short of its limits lets a clean design extrapolate silently.¹²

Failure modes teams check for

• View mismatches. A LEF pin moved without a GDS update, or a Liberty function that disagrees with the netlist, shows up as layout-versus-schematic failures or wrong simulation.
• Corner gaps. Setup is usually worst at slow corners and hold at fast ones; signing off with too few corners hides failures that silicon will find.
• Threshold mixing. Merging libraries characterized with different delay or slew thresholds without a derate shifts every lookup.
• Characterization holes. A missing arc (an unlisted when-condition or a non-unate arc treated as unate) creates timing that STA never checks.

Bilinear interpolation, precisely

With the bracketing indices $s_i, s_{i+1}$ and $c_j, c_{j+1}$, and the fractions $u$ and $v$ defined above, the lookup is²¹²⁰

Expanding gives $d = k_0 + k_u\,u + k_v\,v + k_{uv}\,uv$, with

• $k_0 = y_{00}$
• $k_u = y_{10} - y_{00}$
• $k_v = y_{01} - y_{00}$
• $k_{uv} = y_{11} - y_{10} - y_{01} + y_{00}$

Along a line of constant $u$ or constant $v$ the function is linear; along a diagonal it is quadratic.²¹ The twist term $k_{uv}$ is the cross-sensitivity: how much more load costs when the input is slow. For the worked example it is $121.1 - 84.7 - 90.3 + 56.6 = 2.7\,\mathrm{ps}$, small compared with the first-order terms, which is why the surface looks nearly planar inside one cell.

Interpolation error

Linear interpolation between points $h$ apart has error bounded by roughly $h^2/8$ times the second derivative along that axis. Delay against load is close to linear at large loads, so the load-axis error is small there. It is largest at small slews and loads, where the cell’s intrinsic delay and the input slope effect dominate and the surface curves. Geometric spacing of the index points (about 2.3× steps on SKY130’s slew axis, 2.7× on inv_1’s load axis) concentrates points where curvature is highest.¹² The weights, however, are linear in the raw index values. A point halfway between two load indices on a log scale (their geometric mean) gets a weight well below 0.5: for inv_1’s 3.57–9.52 fF interval, the geometric midpoint 5.83 fF gives $v = 0.38$.

Extrapolation, and why the clamp matters

OpenSTA’s index search returns $n-2$ for any value beyond the last index, and 0 for any value below the first.²⁰ The fraction is not clamped, so $u > 1$ or $v > 1$ extends the bilinear surface of the edge cell. For inv_1 at 50 ps and 300 fF (1.65× max_capacitance) this gives about 1.73 ns. Whether that is optimistic or pessimistic depends on the curvature the grid never saw, which is why libraries end the grid at the design-rule limits, and why flows treat a limit violation as something to repair rather than a number to trust.²⁵

Effective drive resistance from a table

Reading the table as $d \approx d_0(s) + R_{\mathrm{eff}}\,C$ recovers the simple RC model from the Speed and power chapter. Taking the slope between two large-load columns along the fastest row:

• inv_1 rise: $(401.7 - 162.9)/(67.9 - 25.4) = 5.6\,\mathrm{ps/fF}$, so $R_{\mathrm{eff}} \approx 5.6\,\mathrm{k\Omega}$.
• inv_1 fall: $(239.6 - 98.3)/(67.9 - 25.4) = 3.3\,\mathrm{k\Omega}$. The NMOS pull-down is stronger than the PMOS pull-up even with the PMOS 1.5× wider.
• inv_4 rise: $(338.9 - 120.2)/(174.6 - 54.1) = 1.8\,\mathrm{k\Omega}$.

¹⁴ The ratios tell you how the devices scale inside the cell, and the intercepts $d_0(s)$ tell you how much of the delay is the input slope rather than the load.

Why NLDM is not enough at advanced nodes

NLDM assumes the output drives a lumped capacitor and that a ramp with the tabulated slew is a good stand-in for the real waveform. Both fail when wire resistance is significant: the driver sees an effective capacitance smaller than the total, and the far-end waveform has a long tail. Current-source models store the output current as a function of time per slew/load point, so the tool can integrate it into the actual RC network.¹⁸ The cost of CCS is tables of waveforms instead of scalars and a slower delay calculator.

Characterizing a constraint

Setup time is found by a search per (clock slew, data slew) point:

1. Fix both slews.
2. Launch D at a time offset from the clock edge, and bisect on that offset until the flop either fails to capture or its CLK→Q delay grows past a set degradation. SKY130 uses 10%, recorded as violation_delay_degrade_pct.¹⁴
3. Repeat for hold, searching from the other side.

Each table entry needs a whole search of transient simulations, which is why constraint tables are coarse (3 × 3 in dfxtp_1). The degradation threshold is a library-wide choice: a tighter one leaves more margin, a looser one more usable time.