Transistors · Optional deep dive

Bands, doping and the p-n junction

Why does silicon act like a switch at all? This optional chapter looks inside the material. A pinch of other elements lets silicon carry electricity only where and when we want.

Electrons in silicon sit in energy bands with a gap between them. Doping adds free electrons (n-type) or holes (p-type). Where n-type and p-type regions meet, a junction forms that lets current flow one way, and the MOSFET is built on that idea.

Band diagrams, the Fermi level, doping and carrier concentration, the p-n junction under bias, and the MOS capacitor from accumulation to inversion: the physics behind threshold voltage.

This chapter is optional. In The switch, a voltage on the gate pulled electrons into a thin bridge. This chapter asks why that works at all. The answer is hidden inside silicon itself.

Silicon is a . Metal carries electricity easily, and glass hardly carries it at all. Silicon sits in between, and we can change how much it carries on purpose. That is what makes it so good for switches.

Some of this was found by accident. In 1940, Russell Ohl at Bell Labs saw a slab of silicon make electricity when light hit it. Two parts of the slab held different traces of other elements, and the border between them did the trick.

This chapter is optional. It explains the physics behind the switch chapter’s claim that a gate voltage “forms a channel.” You can use transistors without it, but it is where threshold voltage, leakage and many of the trade-offs in later chapters come from.

The chapter builds up in four steps:

  1. Bands. Why silicon is a rather than a metal or an insulator, in terms of the energies its electrons are allowed to have.
  2. Doping. How adding about one foreign atom per million silicon atoms gives silicon extra free electrons or extra holes.
  3. The p-n junction. What happens where the two kinds of silicon meet, and why it conducts one way only. Every transistor’s source and drain is one.
  4. The MOS capacitor. How a gate voltage turns the surface of p-type silicon into a thin n-type layer, and the voltage at which that happens: the threshold voltage.

The idea of controlling a semiconductor with a nearby electrode is old. Julius Lilienfeld patented a field-effect transistor in 1930 and Oskar Heil described a recognizably modern one in 1935, but it took many more innovations to make one that worked. The missing piece was a clean interface between silicon and its oxide. In 1959 Mohamed Atalla and Dawon Kahng at Bell Labs found that thermally grown silicon dioxide greatly reduced the electrical defects at the silicon surface, and built the first successful metal-oxide-semiconductor transistor.

This chapter is optional. You know a MOSFET as a switch with a threshold voltage. Here we derive that threshold from the electrostatics of the gate stack:

VT=Vfb+2ϕB+2qNaεs⋅2ϕBCoxV_{\mathrm{T}} = V_{\mathrm{fb}} + 2\phi_{\mathrm{B}} + \frac{\sqrt{2qN_{\mathrm{a}}\varepsilon_{\mathrm{s}} \cdot 2\phi_{\mathrm{B}}}}{C_{\mathrm{ox}}}

and show what sets each term: gate work function and oxide charge, body doping through the Fermi level, and the depletion charge the gate has to support. Along the way we need carrier statistics (how doping positions the Fermi level), the p-n junction (which isolates every source and drain), and the MOS capacitor from accumulation to inversion.

The treatment is the classic long-channel one. It is the reference the I-V curve and Shrinking chapters correct for short channels, quantum confinement and multi-gate geometries. Three numbers to carry through: silicon’s band gap of 1.12 eV, an intrinsic carrier density of about 1010 cm−310^{10}\,\mathrm{cm^{-3}}, and the thermal voltage kT/q≈25.9 mVkT/q \approx 25.9\,\mathrm{mV} at 300 K.

1 · Bandssilicon bodysourcedrainjunctionjunctiongateoxidechannel (inversion)semiconductor: E_g = 1.12 eV
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Step 1, bands: the energies silicon’s electrons may have, and the gap between them, make it a semiconductor.

The chapter’s four steps, each mapped to the part of an NMOS transistor it explains (cross-section, not to scale).Share freely with credit: ‘Figure from chipfieldguide.com’

Electrons in silicon can only have certain amounts of energy. These form two bands, like the two floors of the garage.

The lower band is full. Its electrons are the glue that holds the atoms together, so none can move. The upper band is almost empty. An electron that gets up there is free to roam.

Between them is the : a jump an electron must make in one go to get free. In a metal there is no jump to make, so metals always carry electricity. In glass the jump is so big that almost no electron makes it. Silicon’s jump is in between.

Heat makes atoms jiggle, and that knocks a few electrons across. Each one leaves an empty spot behind, called a . A neighbor can hop into it, so the hole moves around like a bubble in water. But only about one atom in five trillion loses an electron this way. So pure silicon barely carries electricity.

Each silicon atom shares its four outer electrons with four neighbors, forming covalent bonds; in the crystal every atom has exactly four nearest neighbors. Quantum mechanics says the electrons in such a crystal can only have energies inside certain bands. Two of them decide how silicon conducts:

  • The , filled by the bonding electrons. Its top edge is written EvE_{\mathrm{v}}.
  • The , nearly empty. Its bottom edge is EcE_{\mathrm{c}}.

The gap between them, the Eg=Ec−EvE_{\mathrm{g}} = E_{\mathrm{c}} - E_{\mathrm{v}}, is 1.12 eV for silicon. (An electron-volt, eV, is the energy an electron gains crossing one volt.) Other semiconductors span a wide range: germanium 0.67 eV, gallium arsenide 1.42 eV, diamond 6.0 eV.

A completely full band and a completely empty band both carry no current, just as nothing flows in a full or an empty jar. A metal has a partly filled band, which is why it conducts so well. An insulator has the same layout as a semiconductor with a much bigger gap.

When an electron is lifted into the conduction band it leaves a vacancy in the valence band. That vacancy, a , behaves like a particle with positive charge. Holes carry current just as electrons do, but in silicon they are slower: the mobility (drift speed per unit electric field) is about 1,400 cm²/V·s for electrons and 470 cm²/V·s for holes. That asymmetry comes back in CMOS logic, where PMOS transistors, which conduct with holes, are made wider.

How many carriers, and the Fermi level

Thermal energy at room temperature, written kTkT, is about 0.026 eV, more than forty times smaller than silicon’s gap. So heat lifts very few electrons across. In pure (intrinsic) silicon the nin_{\mathrm{i}} is about 101010^{10} electrons per cm³, with an equal number of holes. A cubic centimeter of silicon holds 5×10225 \times 10^{22} atoms, so only one atom in about five trillion has contributed a free electron.

To describe which states are filled, physicists use the EFE_{\mathrm{F}}: the energy at which a state has a 50% chance of being occupied. The occupancy falls off exponentially above it and approaches 100% below it, over a range of a few kTkT. In intrinsic silicon EFE_{\mathrm{F}} sits very close to the middle of the gap. The sections below are mostly about moving it.

The occupancy of a state at energy EE is the Fermi function

f(E)=11+e(E−EF)/kTf(E) = \frac{1}{1 + e^{(E - E_{\mathrm{F}})/kT}}

More than a few kTkT above EFE_{\mathrm{F}} it reduces to a Boltzmann exponential, and integrating it against the density of states gives the carrier densities in compact form:

  • n=Nc e−(Ec−EF)/kTp=Nv e−(EF−Ev)/kT\begin{aligned} n &= N_{\mathrm{c}}\, e^{-(E_{\mathrm{c}} - E_{\mathrm{F}})/kT} \\ p &= N_{\mathrm{v}}\, e^{-(E_{\mathrm{F}} - E_{\mathrm{v}})/kT} \end{aligned}
    with effective densities of states Nc=2.8×1019N_{\mathrm{c}} = 2.8 \times 10^{19} and Nv=1.04×1019 cm−3N_{\mathrm{v}} = 1.04 \times 10^{19}\,\mathrm{cm^{-3}} for silicon at 300 K.
  • Multiplying them removes EFE_{\mathrm{F}}:
    np=ni2=NcNv e−Eg/kTnp = n_{\mathrm{i}}^2 = N_{\mathrm{c}} N_{\mathrm{v}}\, e^{-E_{\mathrm{g}}/kT}
    This mass-action law holds at equilibrium whether or not dopants are present.
  • The intrinsic level EiE_{\mathrm{i}}, where n=p=nin = p = n_{\mathrm{i}}, sits at midgap plus (kT/2)ln⁡(Nv/Nc)(kT/2)\ln(N_{\mathrm{v}}/N_{\mathrm{c}}), about 13 meV below midgap in silicon. Most hand analysis, and this chapter’s simulation, treats it as midgap.

Hu uses ni≈1010 cm−3n_{\mathrm{i}} \approx 10^{10}\,\mathrm{cm^{-3}}; the modern measured value at 300 K is 9.65×109 cm−39.65 \times 10^9\,\mathrm{cm^{-3}}. The difference shifts a built-in potential by only about 2 mV, but the temperature dependence is large: ni∝T3/2e−Eg/2kTn_{\mathrm{i}} \propto T^{3/2} e^{-E_{\mathrm{g}}/2kT}, so it roughly doubles every 9 °C near room temperature (from the formula with Eg=1.12 eVE_{\mathrm{g}} = 1.12\,\mathrm{eV}). Anything proportional to ni2n_{\mathrm{i}}^2, such as junction leakage, quadruples over the same step.

Two details matter later. First, silicon’s gap is indirect, so it absorbs and emits light poorly compared with direct-gap materials like GaAs. Second, hole mobility is about a third of electron mobility (470 vs 1,400 cm²/V·s in lightly doped silicon), partly because of the larger hole effective mass. Both are bulk numbers; in a MOSFET’s inversion layer the mobilities are lower, because of surface-roughness scattering.

+−no voltageconduction bandvalence bandband gap 1.12 eV○ hole
Material
Voltage across it

Silicon at 300 K: n_i ≈ 1.0×10¹⁰ per cm³, one atom in 5 trillion.

Band diagrams (energy upward). Filled dots are electrons, open dots holes; for silicon each pair stands for ten times more carriers. The insulator’s gap is not to scale.Share freely with credit: ‘Figure from chipfieldguide.com’

Pure silicon has far too few free electrons to be useful. fixes that: you swap a few silicon atoms for atoms of another element.

Phosphorus brings a spare electron, so its silicon is , for negative. Boron is one electron short, which leaves a hole. Its silicon is , for positive.

The amounts are tiny: about one added atom for every million silicon atoms. That’s like one person in a big city. Yet it gives the silicon millions of times more free electrons or holes.

replaces a small fraction of silicon atoms with atoms from a neighboring column of the periodic table.

  • Donors are group V elements (phosphorus, arsenic, antimony) with five outer electrons. The fifth electron is bound so weakly, 39–54 meV depending on the element, that room-temperature heat (kT≈26 meVkT \approx 26\,\mathrm{meV}) frees nearly all of them. The result is silicon.
  • Acceptors are group III elements, almost always boron (45 meV), which complete their bonds by taking an electron from the valence band, creating a hole. The result is silicon.

In n-type silicon electrons are the and holes the minority; in p-type it is the reverse. The two are linked by a simple rule: at equilibrium their product is fixed at ni2n_{\mathrm{i}}^2. A worked example:

QuantityPure siliconDoped with 101710^{17} phosphorus atoms per cm³
Free electrons (nn)101010^{10} per cm³101710^{17} per cm³ (one per donor)
Holes (pp)101010^{10} per cm³(1010)2/1017=103(10^{10})^2/10^{17} = 10^3 per cm³
Dopant share of atoms01017/(5×1022)10^{17}/(5 \times 10^{22}) = 1 in 500,000
Fermi levelMid-gapAbout 0.15 eV below EcE_{\mathrm{c}}

The Fermi level figure is from Hu’s worked example; the atom density is from the Ioffe data tables. Doping 10 million times more electrons into the silicon pushes the holes down 10 million times: the extra electrons fill most of them.

Doping also has a cost. The ionized dopant atoms are charged obstacles that scatter carriers, so mobility falls as doping rises. And doping is done locally, region by region: a fab implants dopant ions into the areas left open by a patterned mask, then heats (anneals) the wafer to move them into the crystal lattice and repair the damage. The Making them chapter covers how.

With full ionization, charge neutrality is n+Na=p+Ndn + N_{\mathrm{a}} = p + N_{\mathrm{d}}. Combined with np=ni2np = n_{\mathrm{i}}^2 it gives the exact majority density

n=Nd−Na2+(Nd−Na2)2+ni2n = \frac{N_{\mathrm{d}} - N_{\mathrm{a}}}{2} + \sqrt{\left(\frac{N_{\mathrm{d}} - N_{\mathrm{a}}}{2}\right)^2 + n_{\mathrm{i}}^2}

which reduces to n≈Nd−Nan \approx N_{\mathrm{d}} - N_{\mathrm{a}} whenever the net doping is well above nin_{\mathrm{i}}. Counter-doping (compensation) is routine: wells, threshold-adjust implants and halos are all layered on top of each other, and only the net doping sets the carriers, while the total doping sets impurity scattering.

The Fermi level follows from the Boltzmann form: EF−Ei=kTln⁡(n/ni)E_{\mathrm{F}} - E_{\mathrm{i}} = kT \ln(n/n_{\mathrm{i}}) for n-type, and Ei−EF=kTln⁡(p/ni)≡qϕBE_{\mathrm{i}} - E_{\mathrm{F}} = kT \ln(p/n_{\mathrm{i}}) \equiv q\phi_{\mathrm{B}} for p-type. Each decade of doping moves EFE_{\mathrm{F}} by kTln⁡10≈60 meVkT \ln 10 \approx 60\,\mathrm{meV}. That logarithm is why doping is such a gentle knob on band positions and such a strong knob on carrier densities.

Where the simple model stops:

  • Degenerate doping. The Boltzmann form is only valid when EFE_{\mathrm{F}} is more than a few kTkT inside the gap. Since Nc=2.8×1019 cm−3N_{\mathrm{c}} = 2.8 \times 10^{19}\,\mathrm{cm^{-3}}, donor levels of around 101910^{19} and above, typical of source/drain regions, put EFE_{\mathrm{F}} at or into the band. Full Fermi-Dirac statistics, incomplete ionization and band-gap narrowing then matter. The simulation stops at 101810^{18} to stay inside the simple model.
  • Temperature extremes. At cryogenic temperatures dopants freeze out (nn falls below NdN_{\mathrm{d}}); at high temperatures nin_{\mathrm{i}} catches up with the doping and the material turns effectively intrinsic.

In a real process, doping is the main knob for threshold flavors. SKY130’s low-VTV_{\mathrm{T}} and high-VTV_{\mathrm{T}} 1.8 V transistors have cross-sections identical to the standard devices except for the VTV_{\mathrm{T}}-adjust implants.

+−SiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiintrinsic silicon: four bonds per atom
Dopant
Voltage across it

Each silicon atom shares its four outer electrons with its four neighbors in covalent bonds. Pick a dopant.

A flat sketch of the silicon crystal with one dopant atom. The dopant share is exaggerated: real doping is roughly one atom in a million.Share freely with credit: ‘Figure from chipfieldguide.com’

Now put n-type silicon right next to p-type silicon. The border between them is a . In a chip, both sides are parts of one crystal, just doped differently.

Free electrons and holes wander across the border and cancel each other out. That leaves a thin empty zone. The added atoms stay behind in it, now charged, and they push back like a hill. So the mixing stops.

Now push with a voltage, an electric push like a battery’s. Push one way and the hill shrinks. Electricity flows easily once the push reaches about 0.6 volts. Push the other way and the hill grows, so only a tiny trickle gets through.

So a junction is a one-way door for electricity, called a diode. LEDs and solar cells are junctions too. In a transistor, these one-way doors keep the source and drain sealed off from each other, until the gate opens a path.

Where p-type and n-type regions meet, electrons diffuse from the n side into the p side and holes diffuse the other way. They leave behind uncovered ionized dopants, positive donors on the n side and negative acceptors on the p side, and the field between these fixed charges pushes back. Equilibrium arrives when the field’s pull (drift) exactly balances the diffusion.

Three results describe the junction:

  • A depletion region forms around the junction, nearly empty of mobile carriers. It reaches mostly into the more lightly doped side, because that side must deplete a wider slab to uncover the same total charge. At 1017 cm−310^{17}\,\mathrm{cm^{-3}} on the light side it is about 0.1 µm wide.
  • A , roughly 0.6–1 V in silicon depending on doping, appears across it. In a band diagram the bands bend by that amount across the depletion region while the Fermi level stays flat: at equilibrium there is no net current anywhere.
  • Rectification. A forward bias VV lowers the barrier by VV, and current rises exponentially, about tenfold per 60 mV at room temperature. That is why silicon diodes seem to “turn on” around 0.6 V. A reverse bias raises the barrier by VV and widens the depletion region; the current is a tiny, nearly constant leakage, until the field gets strong enough for breakdown.

The depletion region acts like the insulator in a capacitor, with the neutral regions on each side as the plates. This junction capacitance shrinks as reverse bias widens the depletion region. It loads every transistor’s source and drain and slows circuits down, which is why it is kept small by limiting junction area and doping. You’ll meet it again in Speed and power.

Under the depletion approximation (neutral regions perfectly neutral, depletion region fully depleted, sharp edges at −xp-x_{\mathrm{p}} and xnx_{\mathrm{n}}), Poisson’s equation integrates to a triangular field and two parabolic potential segments. The results, for a junction with applied forward bias VV:

  • ϕbi=kTqln⁡NaNdni2\phi_{\mathrm{bi}} = \frac{kT}{q} \ln\frac{N_{\mathrm{a}} N_{\mathrm{d}}}{n_{\mathrm{i}}^2}
  • W=xn+xp=2εs(ϕbi−V)q(1Na+1Nd)\begin{aligned} W &= x_{\mathrm{n}} + x_{\mathrm{p}} \\ &= \sqrt{\frac{2\varepsilon_{\mathrm{s}}(\phi_{\mathrm{bi}} - V)}{q}\left(\frac{1}{N_{\mathrm{a}}} + \frac{1}{N_{\mathrm{d}}}\right)} \end{aligned}
    with xn/xp=Na/Ndx_{\mathrm{n}}/x_{\mathrm{p}} = N_{\mathrm{a}}/N_{\mathrm{d}} from charge balance
  • Peak field at the metallurgical junction
    Emax=2(ϕbi−V)/WE_{\mathrm{max}} = 2(\phi_{\mathrm{bi}} - V)/W
  • Junction capacitance per area
    C=εs/WC = \varepsilon_{\mathrm{s}}/W

For the simulation’s junction (Na=1017N_{\mathrm{a}} = 10^{17}, Nd=1016 cm−3N_{\mathrm{d}} = 10^{16}\,\mathrm{cm^{-3}}, εr=11.7\varepsilon_{\mathrm{r}} = 11.7): ϕbi=0.774 V\phi_{\mathrm{bi}} = 0.774\,\mathrm{V}, W=0.332 μmW = 0.332\,\mu\mathrm{m} at zero bias with 91% of it (0.302 µm) on the n side. At 3 V reverse, W=0.733 μmW = 0.733\,\mu\mathrm{m} and Emax≈103 kV/cmE_{\mathrm{max}} \approx 103\,\mathrm{kV/cm}.

Under bias the single Fermi level splits into quasi-Fermi levels EFnE_{\mathrm{Fn}} and EFpE_{\mathrm{Fp}}, separated by qVqV and flat across the depletion region. That gives the boundary condition n(−xp)=np0 eqV/kTn(-x_{\mathrm{p}}) = n_{\mathrm{p0}}\, e^{qV/kT} for injected minority carriers, which then diffuse and recombine over a diffusion length L=DτL = \sqrt{D\tau}. Summing both sides gives the ideal diode law

I=I0(eqV/kT−1)I0=Aqni2(DpLpNd+DnLnNa)\begin{aligned} I &= I_{0}\left(e^{qV/kT} - 1\right) \\ I_{0} &= Aqn_{\mathrm{i}}^2\left(\frac{D_{\mathrm{p}}}{L_{\mathrm{p}} N_{\mathrm{d}}} + \frac{D_{\mathrm{n}}}{L_{\mathrm{n}} N_{\mathrm{a}}}\right) \end{aligned}

Three consequences worth keeping:

  • Injection goes mostly into the lighter-doped side; in a one-sided junction one term of I0I_0 dominates.
  • I0∝ni2I_{0} \propto n_{\mathrm{i}}^2, so reverse leakage climbs steeply with temperature. Drain-to-body junction leakage is one of a MOSFET’s three off-state leakage paths, along with subthreshold conduction and gate tunneling.
  • The built-in potential can’t be measured at the terminals. The metal-semiconductor contacts carry their own contact potentials that cancel it, so a shorted diode at equilibrium carries no current.

Breakdown sets the reverse limit: avalanche multiplication when the peak field reaches a critical value, or band-to-band tunneling in heavily doped junctions, which is the basis of Zener diodes.

energy barrier for electronsholes diffuse →← electrons diffusep-typen-type
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p-type silicon, with holes as majority carriers, and n-type, with electrons. Each is neutral on its own.

A p-n junction forming and then biased. Open dots are holes, filled dots electrons, + and − the fixed dopant ions. Not to scale.Share freely with credit: ‘Figure from chipfieldguide.com’

Now for the transistor’s key piece. Start with p-type silicon. Cover it with a very thin layer of glass, then put a plate that carries electricity on top. That plate is the gate. Watch what the gate’s voltage does to the silicon just under the glass.

A small push on the gate shoves the holes away. A bigger one pulls in a thin sheet of electrons. The surface has flipped to n-type, so the sheet is called an .

That sheet of electrons is the bridge from The switch. It joins the source to the drain. The gate voltage where it appears is the .

Engineers pick the threshold on purpose. Too high, and the transistor needs a big push to turn on. Too low, and it never quite turns off. For a transistor that runs on 1.8 volts, about half a volt is common.

A is a gate electrode on a thin insulator (originally silicon dioxide) on a doped silicon body. For an NMOS device the body is p-type. As the gate voltage VgV_{\mathrm{g}} rises, the silicon surface passes through three regimes separated by two landmarks:

Gate voltageSurfaceBands at the surface
Below VfbV_{\mathrm{fb}}Accumulation: extra holes piled at the surfaceBend up
At VfbV_{\mathrm{fb}}: no charge in the siliconFlat
Between VfbV_{\mathrm{fb}} and VTV_{\mathrm{T}}Depletion: holes pushed away, fixed acceptors uncoveredBend down
At VTV_{\mathrm{T}}Threshold: surface electron density equals the bulk hole densityBent down by 2ϕB2\phi_{\mathrm{B}}
Above VTV_{\mathrm{T}}Inversion: a sheet of electrons at the surfaceBend barely more

The threshold definition, surface electron density equal to the body doping, means the conduction band at the surface has come as close to the Fermi level as the valence band is in the bulk. The band bending needed is twice ϕB\phi_{\mathrm{B}}, the distance (in volts) between the Fermi level and mid-gap in the body.

Past threshold something important happens. The surface electron density depends exponentially on the band bending, so a tiny extra bend supplies a lot of electrons. The depletion region stops growing, and each additional volt on the gate goes into inversion charge. The gate and the channel behave like the two plates of a capacitor: charge per area=Cox(Vg−VT)\text{charge per area} = C_{\mathrm{ox}}(V_{\mathrm{g}} - V_{\mathrm{T}}), where CoxC_{\mathrm{ox}} is the oxide capacitance per area. This is only 1–2 nm thick.

What sets the threshold voltage

The is the sum of three pieces: the gate voltage to reach flat band, the band bending 2ϕB2\phi_{\mathrm{B}}, and the voltage dropped across the oxide to hold the depletion charge. So:

  • Body doping: more doping raises VTV_{\mathrm{T}}, because there is more charge to uncover.
  • Oxide thickness: a thinner oxide (bigger CoxC_{\mathrm{ox}}) lowers VTV_{\mathrm{T}}, because less voltage is dropped across it.
  • Gate material: its shifts VfbV_{\mathrm{fb}}. A p-type body is paired with an n+\mathrm{n^+} gate to get a small positive VTV_{\mathrm{T}}; an n-type body (PMOS) with a p+\mathrm{p^+} gate to get a small negative one.
  • Body voltage: raising the source above the body (reverse-biasing that junction) raises VTV_{\mathrm{T}}. This is the , and it matters in stacked transistors.

For scale: the SKY130 open process’s standard 1.8 V NMOS has VT=0.538 VV_{\mathrm{T}} = 0.538\,\mathrm{V} in the typical corner, and its low-VTV_{\mathrm{T}} version, made with a different threshold-adjust implant, 0.434 V.

Take a p-type body with doping NaN_{\mathrm{a}}, oxide capacitance Cox=εox/ToxC_{\mathrm{ox}} = \varepsilon_{\mathrm{ox}}/T_{\mathrm{ox}} and surface potential ϕs\phi_{\mathrm{s}} (band bending, positive downward). Kirchhoff around the gate stack and Gauss at the interface give

Vg=Vfb+ϕs+Vox,Vox=−Qs/CoxV_{\mathrm{g}} = V_{\mathrm{fb}} + \phi_{\mathrm{s}} + V_{\mathrm{ox}}, \qquad V_{\mathrm{ox}} = -Q_{\mathrm{s}}/C_{\mathrm{ox}}

where QsQ_{\mathrm{s}} is all the charge in the silicon per unit area. The threshold computation then goes in three steps:

  1. Band bending at threshold. With n(0)=ni eqϕ(0)/kTn(0) = n_{\mathrm{i}}\, e^{q\phi(0)/kT}, setting the surface electron density to NaN_{\mathrm{a}} gives ϕs=2ϕB\phi_{\mathrm{s}} = 2\phi_{\mathrm{B}}, where ϕB=(kT/q)ln⁡(Na/ni)\phi_{\mathrm{B}} = (kT/q)\ln(N_{\mathrm{a}}/n_{\mathrm{i}}).
  2. Depletion charge. The depletion width at that bending is Wdmax=2εs⋅2ϕB/(qNa)W_{\mathrm{dmax}} = \sqrt{2\varepsilon_{\mathrm{s}} \cdot 2\phi_{\mathrm{B}}/(qN_{\mathrm{a}})}, holding Qdep=−qNaWdmax=−2qNaεs⋅2ϕBQ_{\mathrm{dep}} = -qN_{\mathrm{a}} W_{\mathrm{dmax}} = -\sqrt{2qN_{\mathrm{a}}\varepsilon_{\mathrm{s}} \cdot 2\phi_{\mathrm{B}}}. Electrons are still negligible.
  3. Sum the drops.
    VT=Vfb+2ϕB+2qNaεs⋅2ϕBCoxV_{\mathrm{T}} = V_{\mathrm{fb}} + 2\phi_{\mathrm{B}} + \frac{\sqrt{2qN_{\mathrm{a}}\varepsilon_{\mathrm{s}} \cdot 2\phi_{\mathrm{B}}}}{C_{\mathrm{ox}}}

The flat-band voltage is the work-function difference less any oxide charge, Vfb=ψg−ψs−Qox/CoxV_{\mathrm{fb}} = \psi_{\mathrm{g}} - \psi_{\mathrm{s}} - Q_{\mathrm{ox}}/C_{\mathrm{ox}}. For an n+\mathrm{n^+} polysilicon gate ψg\psi_{\mathrm{g}} equals silicon’s electron affinity, 4.05 V, and ψs=4.05 V+(Ec−EF)/q\psi_{\mathrm{s}} = 4.05\,\mathrm{V} + (E_{\mathrm{c}} - E_{\mathrm{F}})/q, so Vfb=−(Ec−EF)/qV_{\mathrm{fb}} = -(E_{\mathrm{c}} - E_{\mathrm{F}})/q in the body.

A worked case (the simulation’s default): Na=1018 cm−3N_{\mathrm{a}} = 10^{18}\,\mathrm{cm^{-3}}, Tox=4 nmT_{\mathrm{ox}} = 4\,\mathrm{nm} SiO2\mathrm{SiO_2}, EiE_{\mathrm{i}} at midgap.

TermExpressionValue
CoxC_{\mathrm{ox}}3.9 ε0/Tox3.9\,\varepsilon_{0}/T_{\mathrm{ox}}0.863 µF/cm²
ϕB\phi_{\mathrm{B}}(kT/q)ln⁡(Na/ni)(kT/q)\ln(N_{\mathrm{a}}/n_{\mathrm{i}})0.476 V
VfbV_{\mathrm{fb}}−(Eg/2q+ϕB)-(E_{\mathrm{g}}/2q + \phi_{\mathrm{B}})−1.036 V
2ϕB2\phi_{\mathrm{B}}0.952 V
∣Qdep∣/Cox|Q_{\mathrm{dep}}|/C_{\mathrm{ox}}2qNaεs⋅2ϕB/Cox\sqrt{2qN_{\mathrm{a}}\varepsilon_{\mathrm{s}} \cdot 2\phi_{\mathrm{B}}}/C_{\mathrm{ox}}0.651 V
VTV_{\mathrm{T}}sum0.568 V
WdmaxW_{\mathrm{dmax}}2εs⋅2ϕB/(qNa)\sqrt{2\varepsilon_{\mathrm{s}} \cdot 2\phi_{\mathrm{B}}/(qN_{\mathrm{a}})}35 nm

Above threshold the depletion charge is pinned near its threshold value, so the charge-control relation Qinv=−Cox(Vg−VT)Q_{\mathrm{inv}} = -C_{\mathrm{ox}}(V_{\mathrm{g}} - V_{\mathrm{T}}) follows. Two refinements apply to real devices:

  • Body effect. A source-to-body reverse bias VsbV_{\mathrm{sb}} adds depletion charge coupled through Cdep=εs/WdmaxC_{\mathrm{dep}} = \varepsilon_{\mathrm{s}}/W_{\mathrm{dmax}}, giving VT≈VT0+αVsbV_{\mathrm{T}} \approx V_{\mathrm{T0}} + \alpha V_{\mathrm{sb}} with α≈3Toxe/Wdmax\alpha \approx 3T_{\mathrm{oxe}}/W_{\mathrm{dmax}} (3 being roughly 11.7/3.9, the ratio of dielectric constants). Steep retrograde doping, a light surface layer over a heavy one, pins WdmaxW_{\mathrm{dmax}} and reduces α\alpha.
  • Electrical oxide thickness. Gate depletion in a poly gate and the finite inversion-layer thickness each add about a third of their thickness: Toxe=Tox+Wdpoly/3+Tinv/3T_{\mathrm{oxe}} = T_{\mathrm{ox}} + W_{\mathrm{dpoly}}/3 + T_{\mathrm{inv}}/3. Metal gates remove the first term; the second remains.

The 2ϕB2\phi_{\mathrm{B}} definition is a textbook landmark, not what a datasheet reports. In practice VTV_{\mathrm{T}} is usually extracted as the gate voltage where the drain current reaches a fixed value such as 100 nA×W/L100\,\mathrm{nA} \times W/L.

gate (n+)V_g = −1.04 Voxide−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−p-type body, N_a = 10¹⁸ cm⁻³
Gate voltage V_g

Flat band (V_fb = −1.04 V for an n+ gate on this body): no charge in the silicon, every acceptor matched by its hole.

A MOS capacitor: n+ gate, 4 nm oxide, p-type body with 10¹⁸ acceptors per cm³ (the chapter’s worked example). Depths to scale; the marks on the gate grow with the charge it holds.Share freely with credit: ‘Figure from chipfieldguide.com’
−10+1+2volts on the gateSKY1300.54 V−1.04flat bandV_fb+0.95band bend2φ_B+0.65depletionQ_dep/C_ox0.57 V= thresholdV_T

V_T = 0.57 V. Depletion term 0.65 V: it grows with doping and with oxide thickness.

The threshold voltage as a sum of three terms, for an n+ gate on a p-type body (the chapter’s long-channel model). The dashed line is SKY130’s real 1.8 V NMOS, for scale.Share freely with credit: ‘Figure from chipfieldguide.com’

The simulation draws the two energy bands with the gap between them. Filled dots are free electrons. Open dots are holes.

In Doped silicon, drag the slider left to add boron-like atoms, or right to add phosphorus-like atoms. Watch the dots change. The dashed orange fill line shows how full the bands are. It rises as you add free electrons and drops as you add holes.

In p-n junction, drag the push slider. Watch the hill between the two sides shrink or grow, and the empty zone with it.

The simulation draws band diagrams in three modes. Filled dots are electrons, open dots holes, and each dot stands for a factor of ten in concentration, so the pictures stay readable over 16 orders of magnitude. Things to try:

  • Doping: move from intrinsic to 101710^{17} donors and check that holes drop to 10310^3 per cm³ as electrons rise. Then go to the p side and watch the Fermi level cross mid-gap.
  • p-n junction: sweep from −3 V to +0.7 V. The depletion width shrinks from about 0.73 µm to 0.10 µm, and the current readout rises about tenfold every 60 mV once you’re forward.
  • MOS capacitor: sweep the gate from −2 V to +2.5 V and watch the surface go from accumulation through depletion to inversion. The lower plot shows electrons at the surface (log scale) with the threshold marked. Then raise the body doping or thicken the oxide and see the threshold move.

Everything is analytic: Boltzmann statistics, full ionization, EiE_{\mathrm{i}} at midgap, ni=1010 cm−3n_{\mathrm{i}} = 10^{10}\,\mathrm{cm^{-3}}, εr\varepsilon_{\mathrm{r}} 11.7 (Si) and 3.9 (SiO2\mathrm{SiO_2}), 300 K. The junction uses the depletion approximation with Na=1017N_{\mathrm{a}} = 10^{17} and Nd=1016N_{\mathrm{d}} = 10^{16}. The MOS mode solves the exact one-dimensional charge equation for ϕs\phi_{\mathrm{s}} (see Under the hood), so it is not built on the threshold formula it reports. Experiments:

  • Compare the solved inversion charge with Cox(Vg−VT)C_{\mathrm{ox}}(V_{\mathrm{g}} - V_{\mathrm{T}}). At the default and Vg=2.5 VV_{\mathrm{g}} = 2.5\,\mathrm{V} the model gives Qinv/q≈9.3×1012 cm−2Q_{\mathrm{inv}}/q \approx 9.3 \times 10^{12}\,\mathrm{cm^{-2}} against 1.04×10131.04 \times 10^{13} from the formula: ϕs\phi_{\mathrm{s}} keeps rising past 2ϕB2\phi_{\mathrm{B}} by several kTkT, which the formula ignores.
  • On the log plot, the slope below VTV_{\mathrm{T}} is the subthreshold behavior: surface electron density rises by a decade per m×60 mVm \times 60\,\mathrm{mV}, where m=1+Cdep/Coxm = 1 + C_{\mathrm{dep}}/C_{\mathrm{ox}}. Thin the oxide and watch it steepen.
  • Drop the body doping to 1016.510^{16.5} with a thin oxide: VTV_{\mathrm{T}} goes negative. An n+\mathrm{n^+} gate on a lightly doped p body makes a depletion-mode (normally on) device, which is why the doping and the gate work function have to be chosen together.
  • In the junction mode, check that the depletion width scales as ϕbi−V\sqrt{\phi_{\mathrm{bi}} - V} and that xn/xpx_{\mathrm{n}}/x_{\mathrm{p}} stays at Na/Nd=10N_{\mathrm{a}}/N_{\mathrm{d}} = 10.
Loading simulation…
Silicon band gap
1.12 eV
Free carriers in pure Si (300 K)
~10¹⁰ /cm³
Silicon atoms
5 × 10²² /cm³
SKY130 1.8 V NMOS threshold
0.538 V

These numbers come from a chip textbook, a table of silicon facts and a real chipmaker’s recipe. What they mean:

  • The band gap is 1.12 eV. An eV (electron-volt) is the energy one electron gets from a push of one volt.
  • Pure silicon barely carries electricity. A sugar-cube-sized piece has about 50,000 billion billion atoms, but only about 10 billion free electrons. That’s one in five trillion.
  • A pinch of doping changes everything. Swap one atom in a million and you get millions of times more free electrons.
  • The hill at a junction is less than a volt. That’s why a silicon diode needs a push of about 0.6 volts before electricity really flows.
  • A real transistor turns on at about half a volt. Engineers chose that by adjusting the doping under the gate.
QuantityValueWhy it matters
Band gap: Ge / Si / GaAs / diamond0.67 / 1.12 / 1.42 / 6.0 eVSets intrinsic carriers and leakage
Intrinsic carrier density, Si, 300 K≈1010 cm−3\approx 10^{10}\,\mathrm{cm^{-3}} (9.65×1099.65 \times 10^9 measured)Reference point for every doping calculation
Dopant binding energy: P / As / B44 / 54 / 45 meVAbout 2kT2kT or less, so nearly all are ionized at room temperature
Mobility in Si: electrons / holes1,400 / 470 cm²/V·sPMOS needs more width for the same current
Depletion width at 1017 cm−310^{17}\,\mathrm{cm^{-3}}≈0.1 µmSets junction capacitance
Diode current vs forward voltage×10 per 60 mVThe same exponential governs subthreshold leakage
SKY130 1.8 V NMOS VTV_{\mathrm{T}}: standard / low-VTV_{\mathrm{T}}0.538 / 0.434 VTwo flavors from one structure, by implant

The SKY130 documentation compares its model against e-test specs. For the 1.8 V NMOS (W/L = 7/8 µm) the extracted threshold is 0.538 V typical, 0.520 V fast and 0.557 V slow; the low-VTV_{\mathrm{T}} device is 0.434 V typical. The two share a cross-section and differ only in the VTV_{\mathrm{T}}-adjust implant. The spread between corners (about ±20–25 mV) is smaller than the 100 mV gap between flavors, which is what makes multi-VTV_{\mathrm{T}} libraries useful.

Computed with the simulation’s model (illustrative, uniform doping, 300 K):

CaseResult
EF−EiE_{\mathrm{F}} - E_{\mathrm{i}} for Nd=1016N_{\mathrm{d}} = 10^{16} / 101710^{17} / 101810^{18}0.357 / 0.417 / 0.476 eV
Junction Na=1017N_{\mathrm{a}} = 10^{17}, Nd=1016N_{\mathrm{d}} = 10^{16}: ϕbi\phi_{\mathrm{bi}}0.774 V
Same junction: WW at −3 / 0 / +0.6 / +0.7 V0.733 / 0.332 / 0.157 / 0.102 µm
Same junction: I/I0I/I_0 at +0.6 / +0.7 V1.2×10101.2 \times 10^{10} / 5.8×10115.8 \times 10^{11}
MOS VTV_{\mathrm{T}}, Na=1017N_{\mathrm{a}} = 10^{17}: ToxT_{\mathrm{ox}} 1.5 / 4 / 8 nm−0.07 / 0.05 / 0.24 V
MOS VTV_{\mathrm{T}}, Na=1018N_{\mathrm{a}} = 10^{18}: ToxT_{\mathrm{ox}} 1.5 / 4 / 8 nm0.16 / 0.57 / 1.22 V
MOS at VTV_{\mathrm{T}} (Na=1018N_{\mathrm{a}} = 10^{18}, 4 nm): Qinv/qQ_{\mathrm{inv}}/q≈5×1010 cm−2\approx 5 \times 10^{10}\,\mathrm{cm^{-2}}

Note the sensitivity: at 1018 cm−310^{18}\,\mathrm{cm^{-3}} the depletion term is the biggest lever on VTV_{\mathrm{T}}, and it scales linearly with ToxT_{\mathrm{ox}}. That is why oxide-thickness control is a threshold-control problem as much as a capacitance one.

Low or high threshold? A low threshold turns on with a smaller push, so the transistor can be faster. But it never fully shuts off, so it leaks power all the time. A high threshold leaks less but is slower. Chip designers get several kinds and mix them.

Thin or thick glass? Thinner glass gives the gate a stronger grip. But once it’s only a few atoms thick, electrons start to slip straight through it.

Too few atoms to count on. In the tiniest transistors, the silicon under the gate holds only a few dozen added atoms. The exact number changes by chance from one transistor to the next. So transistors that should be twins aren’t quite the same. Newer transistor shapes avoid relying on that doping.

  • Threshold: speed against leakage. A lower VTV_{\mathrm{T}} gives more drive current at a given supply, but below threshold the current doesn’t drop to zero; it falls by about a factor of ten for every 60–100 mV, so a lower VTV_{\mathrm{T}} means exponentially more off-state leakage. Processes therefore offer several VTV_{\mathrm{T}} flavors from the same structure, made with different implants. See Speed and power.
  • Doping: control against mobility and capacitance. Heavier body doping keeps depletion regions thin, which helps the gate keep control of a short channel, but it raises VTV_{\mathrm{T}}, lowers mobility through impurity scattering, and increases junction capacitance.
  • Oxide: control against tunneling. A thinner oxide raises CoxC_{\mathrm{ox}}, which lowers VTV_{\mathrm{T}}, strengthens the gate and shrinks the body effect, but below about 1.5 nm SiO2\mathrm{SiO_2} electrons tunnel straight through: 1.2 nm of SiO2\mathrm{SiO_2} leaks about 1,000 A per cm². High-k dielectrics such as HfO2\mathrm{HfO_2} give the same capacitance with a physically thicker film.
  • Variation. Random dopant fluctuation, the chance variation in how many dopant atoms sit under each small gate, causes significant threshold differences between nominally identical transistors.
  • Temperature. Heat raises nin_{\mathrm{i}} steeply, which raises junction leakage. Since ϕB=(kT/q)ln⁡(Na/ni)\phi_{\mathrm{B}} = (kT/q)\ln(N_{\mathrm{a}}/n_{\mathrm{i}}) shrinks as nin_{\mathrm{i}} grows, VTV_{\mathrm{T}} also falls as a chip heats up, adding more subthreshold leakage on top.
  • Choosing VTV_{\mathrm{T}}. Subthreshold current goes as 10(Vgs−VT)/S10^{(V_{\mathrm{gs}} - V_{\mathrm{T}})/S} with swing S=η⋅60 mV/decadeS = \eta \cdot 60\,\mathrm{mV/decade} at 300 K, η≥1\eta \ge 1 set by Cdep/CoxeC_{\mathrm{dep}}/C_{\mathrm{oxe}} (and interface states). Every 100 mV of VTV_{\mathrm{T}} reduction at S=100 mV/decadeS = 100\,\mathrm{mV/decade} costs a decade of IoffI_{\mathrm{off}}. Lowering SS, by a thinner oxide or a wider depletion layer, is the preferred way to get both a low VTV_{\mathrm{T}} and a low IoffI_{\mathrm{off}}.
  • Doping profile. A uniform body forces a trade between WdmaxW_{\mathrm{dmax}} (short-channel control wants it small) and VTV_{\mathrm{T}}, mobility and body effect (which want light doping at the surface). Steep retrograde profiles, a light surface layer over a heavily doped one, decouple them: the depletion layer is basically the thickness of the light layer.
  • Random dopant fluctuation, back of the envelope. At Na=1018 cm−3N_{\mathrm{a}} = 10^{18}\,\mathrm{cm^{-3}}, Wdmax≈35 nmW_{\mathrm{dmax}} \approx 35\,\mathrm{nm}. Under a 30 nm × 30 nm gate that volume holds 1018×(3×10−6 cm)2×3.5×10−6 cm≈3210^{18} \times (3 \times 10^{-6}\,\mathrm{cm})^2 \times 3.5 \times 10^{-6}\,\mathrm{cm} \approx 32 acceptors. Poisson statistics give σ=32≈5.6\sigma = \sqrt{32} \approx 5.6, an 18% spread in QdepQ_{\mathrm{dep}}. With ∣Qdep∣/Cox≈0.65 V|Q_{\mathrm{dep}}|/C_{\mathrm{ox}} \approx 0.65\,\mathrm{V}, that is on the order of 0.1 V of VTV_{\mathrm{T}} spread (an overestimate, since dopants deep in the depletion region count less, but the scale is right). The general point: σ(VT)\sigma(V_{\mathrm{T}}) from RDF grows as gate area shrinks.
  • Undoped channels and work-function VTV_{\mathrm{T}}. FinFETs were conceived with undoped channels, relying on fin dimensions for gate control, which removes RDF. The cost is that VTV_{\mathrm{T}} must come from the gate work function, which adds process complexity. Light channel doping is an option, at some cost in mobility and RDF: in IBM and GlobalFoundries test wafers at 6×1017 cm−36 \times 10^{17}\,\mathrm{cm^{-3}} about a third of measured variability came from RDF, the rest from fin height, gate length and work-function variation. Metal gates for NMOS and PMOS generally need different metals with work functions near those of n+\mathrm{n^+} and p+\mathrm{p^+} poly.
  • Oxide scaling. SiO2\mathrm{SiO_2} tunneling leakage rises exponentially as it thins (103 A/cm210^3\,\mathrm{A/cm^2} at 1.2 nm). HfO2\mathrm{HfO_2} with an equivalent oxide thickness of 1 nm leaks orders of magnitude less, at the price of chemical reactions with the silicon, lower mobility and more oxide charge, which is why a thin SiO2\mathrm{SiO_2} interlayer remains under the high-k film.
under the gate (top view)28 acceptorsmean 31.5all 1 built−100%−50%N̄+50%+100%count vs mean
Gate (L × W)

28 acceptors (average 32, −11%). 1 built; chance alone predicts a spread of about ±18%.

Random dopant fluctuation: the number of acceptors under the gate follows chance (Poisson) statistics, so its relative spread is 1/√N. Numbers from the chapter’s estimate at 10¹⁸ cm⁻³.Share freely with credit: ‘Figure from chipfieldguide.com’

This part goes deeper, into the math, models and algorithms behind the chapter. It’s written for the Expert level.

Equilibrium as drift balancing diffusion

Every band diagram in this chapter rests on one statement: at equilibrium the electron and hole currents vanish separately, so in every region drift exactly cancels diffusion. With the Einstein relation, that forces the Boltzmann relations

n(x)=ni eqϕ(x)/kTp(x)=ni e−qϕ(x)/kT\begin{aligned} n(x) &= n_{\mathrm{i}}\, e^{q\phi(x)/kT} \\ p(x) &= n_{\mathrm{i}}\, e^{-q\phi(x)/kT} \end{aligned}

with ϕ\phi measured from the intrinsic level, and np=ni2np = n_{\mathrm{i}}^2 everywhere. Under bias, as long as the oxide or the depletion region keeps current small, the same relations hold in quasi-equilibrium. The remaining equation is Poisson’s, dE/dx=ρ/εsdE/dx = \rho/\varepsilon_{\mathrm{s}}.

The depletion approximation and its limits

Substituting the Boltzmann densities into Poisson gives a nonlinear equation. The depletion approximation replaces it with a box: ρ=−qNa\rho = -qN_{\mathrm{a}} or +qNd+qN_{\mathrm{d}} inside the depletion region and zero outside, with sharp edges. The field is then piecewise linear, the potential piecewise parabolic, and charge neutrality plus continuity of ϕ\phi fix xnx_{\mathrm{n}} and xpx_{\mathrm{p}}. The edges are really smeared over a few Debye lengths, LD=εskT/(q2N)L_{\mathrm{D}} = \sqrt{\varepsilon_{\mathrm{s}} kT/(q^2 N)}, about 4 nm at 1018 cm−310^{18}\,\mathrm{cm^{-3}} and 40 nm at 101610^{16} (from the formula). The approximation is good when W≫LDW \gg L_{\mathrm{D}}, which fails near flat band and in weak accumulation; that is exactly where the exact solution below is needed.

The exact MOS charge equation (what the simulation solves)

For a uniformly doped p-type body, multiply Poisson by dϕ/dxd\phi/dx and integrate once from the bulk (ϕ=0\phi = 0, E=0E = 0) to the surface. With β=q/kT\beta = q/kT this gives the surface field, and by Gauss’s law the total silicon charge:

Qs=−sgn(ϕs) 2εskTNa  F(ϕs)Q_{\mathrm{s}} = -\mathrm{sgn}(\phi_{\mathrm{s}})\,\sqrt{2\varepsilon_{\mathrm{s}} kT N_{\mathrm{a}}}\;F(\phi_{\mathrm{s}})
F2=(e−βϕ+βϕ−1)+(niNa)2(eβϕ−βϕ−1)\begin{aligned} F^2 &= \left(e^{-\beta\phi} + \beta\phi - 1\right) \\ &\quad + \left(\frac{n_{\mathrm{i}}}{N_{\mathrm{a}}}\right)^2\left(e^{\beta\phi} - \beta\phi - 1\right) \end{aligned}

The first bracket is the hole and ionized-acceptor contribution and the second is electrons. Each regime appears as one term dominating:

  • Accumulation (ϕs<0\phi_{\mathrm{s}} < 0): e−βϕe^{-\beta\phi} dominates and the hole charge grows as eβ∣ϕ∣/2e^{\beta|\phi|/2}, so ϕs\phi_{\mathrm{s}} barely moves past a few kTkT negative.
  • Depletion: βϕ\beta\phi dominates, recovering Q=−2qNaεsϕsQ = -\sqrt{2qN_{\mathrm{a}}\varepsilon_{\mathrm{s}}\phi_{\mathrm{s}}}, the depletion result.
  • Inversion: the electron term catches up when (ni/Na)2eβϕ≈βϕ(n_{\mathrm{i}}/N_{\mathrm{a}})^2 e^{\beta\phi} \approx \beta\phi, near ϕs=2ϕB\phi_{\mathrm{s}} = 2\phi_{\mathrm{B}}, and then grows as eβϕ/2e^{\beta\phi/2}. That exponential is why ϕs\phi_{\mathrm{s}} pins a few kTkT above 2ϕB2\phi_{\mathrm{B}} and why the depletion width saturates.
1e101e111e121e131e141e150.00.40.81.2surface potential φ_s (V) →|Q_s|/q (cm⁻²)flat bandφ_B2φ_B
Body doping N_a

φ_s = 0.500 V → |Q_s|/q = 2.5e12 cm⁻², electrons negligible, V_g = −0.08 V. Depletion: βφ dominates, |Q| = √(2qN_aε_sφ_s).

|Q_s|/q from the exact charge equation (solid), split into the hole-and-acceptor term (pink, dashed) and the electron term (blue, dashed). n_i = 10¹⁰ cm⁻³, T_ox = 4 nm, n+ gate; V_g = V_fb + φ_s − Q_s/C_ox.Share freely with credit: ‘Figure from chipfieldguide.com’

Since Vg=Vfb+ϕs−Qs(ϕs)/CoxV_{\mathrm{g}} = V_{\mathrm{fb}} + \phi_{\mathrm{s}} - Q_{\mathrm{s}}(\phi_{\mathrm{s}})/C_{\mathrm{ox}} is monotonic in ϕs\phi_{\mathrm{s}}, the simulation finds ϕs\phi_{\mathrm{s}} for each gate voltage by bisection over −0.8 to 1.6 V (60 halvings, far below a microvolt). The inversion charge is the difference between QsQ_{\mathrm{s}} with and without the electron term. Nothing in that loop uses the threshold formula; VTV_{\mathrm{T}} is drawn on the plot only as the textbook landmark to compare against.

Below threshold

In weak inversion the electron sheet density is proportional to eβϕse^{\beta\phi_{\mathrm{s}}}, while ϕs\phi_{\mathrm{s}} follows VgV_{\mathrm{g}} through a capacitive divider: dϕs/dVg=Cox/(Cox+Cdep)d\phi_{\mathrm{s}}/dV_{\mathrm{g}} = C_{\mathrm{ox}}/(C_{\mathrm{ox}} + C_{\mathrm{dep}}). So the current falls a decade for every η×60 mV\eta \times 60\,\mathrm{mV} of gate voltage, with η≈1+Cdep/Coxe\eta \approx 1 + C_{\mathrm{dep}}/C_{\mathrm{oxe}}, larger when interface states add their own capacitance in parallel with CdepC_{\mathrm{dep}}. The same 60 mV is the diode’s per-decade figure: both are kTln⁡10/qkT \ln 10/q, the Boltzmann factor showing through. No conventional MOSFET at room temperature can switch more steeply than that.

How the parameters are measured

The MOS capacitor is also the main measurement structure. Its capacitance–voltage (C–V) curve, measured by adding a small AC signal to a DC gate sweep, is the usual way to determine oxide thickness, substrate doping, flat-band voltage and threshold voltage. In accumulation the structure is just CoxC_{\mathrm{ox}}; in depletion it is CoxC_{\mathrm{ox}} in series with the depletion capacitance, falling as WW grows. In inversion a slow (quasi-static) sweep returns to CoxC_{\mathrm{ox}}, while a high-frequency curve stays low because the inversion charge can’t follow the AC signal. A MOSFET’s source and drain junctions supply that charge quickly, which is why a transistor’s gate C–V follows the quasi-static curve at all frequencies.

Assumptions the simulation makes

  • Boltzmann statistics and full ionization, so doping is capped at 1018 cm−310^{18}\,\mathrm{cm^{-3}}.
  • EiE_{\mathrm{i}} at midgap; ni=1010 cm−3n_{\mathrm{i}} = 10^{10}\,\mathrm{cm^{-3}}; T=300 KT = 300\,\mathrm{K}.
  • Uniform doping, one dimension, no oxide or interface charge, an ideal n+\mathrm{n^+} gate with no depletion.
  • No quantum confinement: a real inversion layer’s electrons sit effectively 1.5–3 nm below the interface, which adds Tinv/3T_{\mathrm{inv}}/3 to the electrical oxide thickness.
  • The junction’s quasi-Fermi levels are drawn flat on each side; diffusion and recombination of the injected carriers are only indicated by dots.
Novice · 0 of 4 correct
  1. Q1Silicon is doped with 101710^{17} donors per cm³ and nin_{\mathrm{i}} is about 101010^{10} per cm³. Roughly how many holes per cm³ are there?

  2. Q2A junction has p-side doping 101910^{19} and n-side doping 101610^{16} per cm³. Where is the depletion region?

  3. Q3What happens to an NMOS threshold voltage if the p-type body is doped more heavily?

  4. Q4Once a MOS capacitor is past threshold, where does extra gate voltage mostly go?

Sources

Show Hide 16 sources
  1. Chapter 1: Electrons and Holes in Semiconductors, Modern Semiconductor Devices for Integrated CircuitsChenming Calvin Hu · UC Berkeley (author’s site) · 2010Bond and band models, Eg = 1.12 eV for Si and other band gaps, donors and acceptors with ionization energies, Fermi function, Nc and Nv, ni ≈ 10¹⁰ cm⁻³, np = ni², Fermi level vs doping.
  2. Chapter 2: Motion and Recombination of Electrons and Holes, Modern Semiconductor Devices for Integrated CircuitsChenming Calvin Hu · UC Berkeley (author’s site) · 2010Mobility values (Si: 1400 cm²/V·s for electrons, 470 for holes) and impurity scattering, which lowers mobility as doping rises.
  3. Chapter 4: PN and Metal–Semiconductor Junctions, Modern Semiconductor Devices for Integrated CircuitsChenming Calvin Hu · UC Berkeley (author’s site) · 2010Built-in potential, depletion width (≈0.1 µm at 10¹⁷ cm⁻³), one-sided junctions, reverse bias, junction capacitance, the diode equation, 60 mV per decade, the ~0.6 V turn-on of Si diodes, breakdown.
  4. Chapter 5: MOS Capacitor, Modern Semiconductor Devices for Integrated CircuitsChenming Calvin Hu · UC Berkeley (author’s site) · 2010Flat band, accumulation, depletion, threshold (ns = Na, φs = 2φB) and inversion; Vfb = ψg − ψs − Qox/Cox; the threshold-voltage equation; Qinv = −Cox(Vg − Vt); gate-body pairing; electrical oxide thickness.
  5. Chapter 6: MOS Transistor, Modern Semiconductor Devices for Integrated CircuitsChenming Calvin Hu · UC Berkeley (author’s site) · 2010Early FET patents (Lilienfeld 1930, Heil 1935), the inversion layer as a 1–2 nm film, the body effect and its coefficient, steep retrograde body doping, implanting and annealing dopants.
  6. Chapter 7: MOSFETs in ICs—Scaling, Leakage, and Other Topics, Modern Semiconductor Devices for Integrated CircuitsChenming Calvin Hu · UC Berkeley (author’s site) · 2010Subthreshold current and swing, the constant-current Vt definition, three leakage paths, oxide tunneling (1.2 nm SiO₂ leaks 10³ A/cm²), high-k and metal gates, random dopant fluctuation, FinFETs.
  7. Lecture 5: PN Junction and MOS Electrostatics (II), PN junction in thermal equilibrium (6.012 Microelectronic Devices and Circuits)MIT OpenCourseWare · 2009Drift balances diffusion in equilibrium; the depletion approximation; built-in potential, xn, xp, total width and peak field; the lightly doped side controls the junction; contact potentials.
  8. Lecture 7: PN Junction and MOS Electrostatics (IV), MOS structure under bias (6.012 Microelectronic Devices and Circuits)MIT OpenCourseWare · 2009Boltzmann relations under bias, depletion width vs gate voltage, flat band, accumulation, the threshold computation in three steps, how Vt depends on doping and oxide, and the charge-control relation QN = −Cox(VGB − VT).
  9. Intrinsic Carrier ConcentrationPVEducationThe accepted value of ni for silicon at 300 K is 9.65 × 10⁹ cm⁻³ (Altermatt).
  10. DopingPVEducationGroup V atoms make n-type silicon and group III atoms make p-type; majority and minority carriers.
  11. Formation of a PN-JunctionPVEducationElectrons and holes diffuse across the junction, exposing ion cores that set up an electric field and a built-in potential.
  12. Si – Silicon: Basic Parameters at 300 KIoffe Physico-Technical Institute · NSM Archive (Physical Properties of Semiconductors)5 × 10²² atoms per cm³, dielectric constant 11.7, electron affinity 4.05 eV, lattice constant 5.431 Å.
  13. Device Details (SKY130 primitive devices)SkyWater Technology and Google · SkyWater SKY130 PDK documentation1.8 V NMOS threshold 0.538 V (TT, W/L = 7/8) and low-Vt NMOS 0.434 V; low- and high-Vt devices differ from the standard ones only by Vt-adjust implants.
  14. 1940: Discovery of the p-n JunctionComputer History Museum, The Silicon EngineRussell Ohl’s silicon sample at Bell Labs; Ohl and Scaff named the n-type and p-type regions and the p-n junction.
  15. 1960: Metal Oxide Semiconductor (MOS) Transistor DemonstratedComputer History Museum, The Silicon EngineAtalla and Kahng at Bell Labs found that thermally grown SiO₂ markedly reduced surface states and built the first successful insulated-gate FET.
  16. Doping gives finFETs threshold controlChris Edwards · Tech Design Forum · 2012FinFETs were conceived with undoped channels; setting Vt through gate work function adds process complexity; light channel doping is an option, with random dopant fluctuation about a third of variability at 6 × 10¹⁷ cm⁻³. Reports IBM and GlobalFoundries’ VLSI 2012 paper, which is not openly available.