The I-V curve

The I-V characteristic is the transistor’s contract with the circuit: $I_{\mathrm{D}}(V_{\mathrm{GS}}, V_{\mathrm{DS}}, V_{\mathrm{BS}})$. Every number a digital designer cares about comes from it. The on-current sets gate delay, the off-current sets standby leakage, and the shape of the curve in between sets how a gate’s output slews and how much current flows while it switches. Analog designers read transconductance and output resistance off the same curves.

The long-channel Shockley square law gives the three regions and a useful first-order picture.¹ Short-channel devices depart from it in predictable ways:

• Velocity saturation flattens the growth of drive current with overdrive.
• Channel-length modulation and DIBL tilt the saturation curves.
• Subthreshold conduction replaces “off” with an exponential tail.²

This chapter works through each effect with its standard hand model, ties the models to open SKY130 data, and ends with how SPICE compact models and threshold-extraction methods turn measured curves into the numbers in a PDK.

By convention the source is the lower-voltage diffusion of an NMOS, so $V_{\mathrm{DS}} \ge 0$. Take the body at the source potential. The operating region follows from comparing $V_{\mathrm{GS}}$ and $V_{\mathrm{GD}}$ with $V_{\mathrm{T}}$.¹

• Cutoff ($V_{\mathrm{GS}} < V_{\mathrm{T}}$): no inversion layer anywhere. The long-channel model sets $I_{\mathrm{D}} = 0$. In reality the device is in weak inversion and conducts a diffusion current that is exponential in $V_{\mathrm{GS}}$ (see “Below threshold”).
• Linear (triode) ($V_{\mathrm{GS}} > V_{\mathrm{T}}$, $V_{\mathrm{GD}} > V_{\mathrm{T}}$): the channel is inverted from source to drain. The local channel voltage $V_{\mathrm{c}}$ rises from 0 to $V_{\mathrm{DS}}$, so the inversion charge per area, $C_{\mathrm{ox}}(V_{\mathrm{GS}} - V_{\mathrm{c}} - V_{\mathrm{T}})$, tapers toward the drain.
• Saturation ($V_{\mathrm{GD}} \le V_{\mathrm{T}}$, i.e. $V_{\mathrm{DS}} \ge V_{\mathrm{GS}} - V_{\mathrm{T}}$): the inversion charge reaches zero at the drain end (pinch-off). The extra $V_{\mathrm{DS}}$ drops across a short depleted region next to the drain, and to first order the current no longer depends on $V_{\mathrm{DS}}$.

A digital gate visits all three regions in every transition. When an inverter’s input rises, the NMOS leaves cutoff and enters saturation, because its drain is still at $V_{\mathrm{DD}}$. It then slides into the linear region as the output falls below $V_{\mathrm{GS}} - V_{\mathrm{T}}$, and the PMOS goes the other way.³ That is why both $I_{\mathrm{on}}$ (a saturation-region number) and the linear-region resistance matter for delay. The Speed and power chapter turns them into delay models.

For PMOS, flip every sign. Hole mobility is about 2–3× lower than electron mobility (120 vs. 350 cm²/V·s in the 0.6 µm example process below), so PMOS devices are drawn wider for matched drive.¹

The gradual-channel approximation treats the channel as a sheet with charge per area $Q(y) = C_{\mathrm{ox}}(V_{\mathrm{GS}} - V_{\mathrm{T}} - V_{\mathrm{c}}(y))$ and constant mobility. Integrating $I_{\mathrm{D}} = W \mu\, Q(y)\, dV_{\mathrm{c}}/dy$ from source to drain gives the Shockley equations:¹⁴

cutoff      VGS < Vt                 ID = 0
linear      VDS < VDSAT              ID = β (VGS − Vt − VDS/2) VDS
saturation  VDS ≥ VDSAT              ID = (β/2) (VGS − Vt)²

β = μ Cox W / L      Cox = εox / tox      VDSAT = VGS − Vt

Three properties of the model are worth keeping in mind, because the short-channel effects attack each one:

1. Square-law drive. $I_{\mathrm{Dsat}} \propto V_{\mathrm{GT}}^2$, with $V_{\mathrm{GT}} = V_{\mathrm{GS}} - V_{\mathrm{T}}$. So the transconductance $g_{\mathrm{m}} = \beta V_{\mathrm{GT}} = 2I_{\mathrm{D}}/V_{\mathrm{GT}}$ grows with bias.
2. $V_{\mathrm{DSAT}} = V_{\mathrm{GT}}$. The knee moves out linearly with overdrive.
3. Flat saturation. $\partial I_{\mathrm{D}}/\partial V_{\mathrm{DS}} = 0$, so the output resistance is infinite.

In MIT’s 6.012 formulation a body-effect factor $\alpha \approx 1$ also appears. It divides $V_{\mathrm{DSAT}}$ and the saturation current, and it is usually close to 1.⁴ Harris’s 0.6 µm example ($t_{\mathrm{ox}} = 100\,\text{Å}$, $\mu_{\mathrm{n}} = 350\,\mathrm{cm^2/V{\cdot}s}$, $V_{\mathrm{T}} = 0.7\,\mathrm{V}$) gives $\mu C_{\mathrm{ox}} \approx 120\,\mu\mathrm{A/V^2}$. A $W/L = 2$ device then carries about 2.2 mA at $V_{\mathrm{GS}} = V_{\mathrm{DS}} = 5\,\mathrm{V}$, which matches the plotted curves for that process.¹ For long channels this is a good model. The next section shows how far it drifts for a 0.15 µm one.

Mobility degradation and velocity saturation

Two high-field effects bend the long-channel curves.²

• Mobility degradation. The vertical field (about $V_{\mathrm{GS}}/t_{\mathrm{ox}}$) presses carriers against the oxide interface, where they scatter more. The effective $\mu$ falls as $V_{\mathrm{GS}}$ rises.
• Velocity saturation. The lateral field (about $V_{\mathrm{DS}}/L$) can’t accelerate carriers past $v_{\mathrm{sat}} \approx 10^7\,\mathrm{cm/s}$ for electrons and $8 \times 10^6\,\mathrm{cm/s}$ for holes.

Compare the two limits:

• Long channel: $I_{\mathrm{Dsat}} = \dfrac{\mu C_{\mathrm{ox}} W}{2L}(V_{\mathrm{GS}} - V_{\mathrm{T}})^2$.
• Fully velocity-saturated: $I_{\mathrm{Dsat}} = W C_{\mathrm{ox}} (V_{\mathrm{GS}} - V_{\mathrm{T}})\, v_{\mathrm{sat}}$.²

The second is linear in overdrive and has no $L$ in it. Once carriers run at $v_{\mathrm{sat}}$, a shorter channel no longer buys more saturation current through the $1/L$ term, only through higher $C_{\mathrm{ox}}$ and lower $V_{\mathrm{T}}$. Real devices are partly saturated, and Sakurai and Newton’s power-law models fit them with an exponent between 1 and 2. Harris gives the $\alpha$-power saturation current and $V_{\mathrm{DSAT}}$ (line 1 below); the linear-region and $\lambda$ terms (lines 2 and 3) are Sakurai and Newton’s:²⁶

IDsat = Pc (β/2) (VGS − Vt)^α        VDSAT = Pv (VGS − Vt)^(α/2)
VDS < VDSAT:  ID = IDsat · (2 − VDS/VDSAT) · (VDS/VDSAT)
VDS ≥ VDSAT:  ID = IDsat · (1 + λ VDS)

Sakurai and Newton’s 1990 report states the limits directly. Their model reduces to Shockley for $n = 2$, and it can also express short-channel theory’s prediction that $V_{\mathrm{DSAT}} \propto V_{\mathrm{GT}}^{0.5}$ and $I_{\mathrm{Dsat}} \propto V_{\mathrm{GT}}$.⁶ Fitted $\alpha$ values sit in between: about 1.3 for a 65 nm process.² Two consequences follow for digital design:

• Drive current grows as about $V_{\mathrm{DD}}^{\alpha}$ rather than $V_{\mathrm{DD}}^2$. Raising the supply buys less speed than the square law suggests.
• $V_{\mathrm{DSAT}}$ is well below $V_{\mathrm{GT}}$. A switching transistor reaches its saturation current at a lower $V_{\mathrm{DS}}$, and the linear region is compressed.

Channel-length modulation

The reverse-biased drain junction’s depletion width $L_{\mathrm{d}}$ grows with $V_{\mathrm{DS}}$, so $L_{\mathrm{eff}} = L - L_{\mathrm{d}}$ shrinks and $I_{\mathrm{D}}$ keeps rising in saturation.² The usual empirical forms are $I_{\mathrm{D}} = \frac{\beta}{2} V_{\mathrm{GT}}^2 (1 + \lambda V_{\mathrm{DS}})$, or $(1 + \lambda(V_{\mathrm{DS}} - V_{\mathrm{DSAT}}))$ in MIT’s 6.012 notation, with $\lambda = 1/V_{\mathrm{A}}$ by analogy to the bipolar Early voltage.⁴ $\lambda$ is not the layout $\lambda$. It is a fitted coefficient, and it grows as $L$ shrinks.² The output resistance follows directly: $r_{\mathrm{o}} = (\partial I_{\mathrm{D}}/\partial V_{\mathrm{DS}})^{-1} \approx 1/(\lambda I_{\mathrm{D}})$.

DIBL and other threshold shifts

$V_{\mathrm{T}}$ isn’t a constant.²

• Body effect. $V_{\mathrm{T}}$ rises with source-to-body reverse bias.
• DIBL. $V_{\mathrm{T}}$ falls with $V_{\mathrm{DS}}$, modeled as $V_{\mathrm{T}}' = V_{\mathrm{T}} - \eta V_{\mathrm{DS}}$.
• Short-channel effect. $V_{\mathrm{T}}$ depends on $L$. Some processes show a reverse short-channel effect, where $V_{\mathrm{T}}$ is higher at short $L$.

In saturation, DIBL raises $I_{\mathrm{D}}$ with $V_{\mathrm{DS}}$ on top of channel-length modulation, so the measured $r_{\mathrm{o}}$ of a short device is lower than $\lambda$ alone predicts. Its biggest effect is below threshold, where a $V_{\mathrm{T}}$ shift becomes an exponential change in current.

In weak inversion the channel potential at the surface tracks $V_{\mathrm{GS}}$ through a capacitive divider (oxide capacitance against depletion capacitance), and drain current is diffusion over the source barrier. The 6.012 derivation gives:⁷

ID ≈ I0 · exp[(VGS − Vt) / (n·kT/q)] · [1 − exp(−VDS / (kT/q))]

n  = 1 + Cdep/Cox            (≈ 1.3–1.7 in practice)
S  = n · (kT/q) · ln 10      ≈ 60·n mV/decade at 300 K
Vt → Vt − η·VDS  (DIBL)       Vt → Vt + γ-term (body effect)

MIT’s notes plot this for a 3 nm oxide and $N_{\mathrm{A}} = 10^{18}\,\mathrm{cm^{-3}}$ device: $n = 1.25$, so 75 mV/decade. They also note that the current at threshold is small next to strong-inversion current even 0.1 V above $V_{\mathrm{T}}$.⁷ Harris quotes $n \approx 1.3\text{–}1.7$ and $S \approx 100\,\mathrm{mV/decade}$ at room temperature, and writes the full expression with DIBL ($\eta$) and body-effect terms.²

For design, the useful form is

adjusted for DIBL at $V_{\mathrm{DS}} = V_{\mathrm{DD}}$. Each $S$ of threshold reduction costs one decade of leakage, and each $S$ of DIBL shift between $V_{\mathrm{DS}} \approx 0$ and $V_{\mathrm{DD}}$ costs another. Temperature attacks twice:

• $kT/q$ grows, so $S$ grows in proportion to absolute temperature.
• $V_{\mathrm{T}}$ falls. So $I_{\mathrm{off}}$ rises steeply with temperature while $I_{\mathrm{on}}$ falls, because mobility drops.²

Subthreshold current isn’t the only leakage. Harris lists gate tunneling (critical once $t_{\mathrm{ox}}$ reached about 10.5 Å at 65 nm) and junction leakage (reverse diode current, band-to-band tunneling and gate-induced drain leakage). It names subthreshold conduction as the dominant source in contemporary transistors.²

Note what a hand model like the $\alpha$-power law does here: nothing. Sakurai and Newton say outright that their model is a rough approximation near and below threshold, which they judged unimportant for delay.⁶ Leakage analysis needs the full all-region compact model.

A device characterization run produces a standard set of sweeps. Each one isolates a parameter:

Things to check when you read one:

• Normalization. µA/µm at what $V_{\mathrm{DD}}$, temperature and corner? An $I_{\mathrm{on}}$ without its conditions is not comparable. Corners shift the curves noticeably. Harris’s example uses ±10% supply and 0–125 °C.²
• Which $V_{\mathrm{T}}$. Linear-extrapolation $V_{\mathrm{T}}$ is skewed by mobility degradation and series resistance. Constant-current $V_{\mathrm{T}}$ depends on the chosen current. Second-derivative and $g_{\mathrm{m}}/I_{\mathrm{D}}$ methods use other definitions again. On 0.18 µm NMOS at $L = 0.2\,\mu\mathrm{m}$, the methods gave 481 mV (linear extrapolation), 490 (second derivative), 520 ($g_{\mathrm{m}}/I_{\mathrm{D}}$) and 501 (constant current).⁸
• Spacing of the output family. With equal $V_{\mathrm{GS}}$ steps, curve spacing that grows with $V_{\mathrm{GS}}$ signals square-law behavior. Spacing that stays roughly constant signals velocity saturation ($g_{\mathrm{m}}$ independent of $V_{\mathrm{GS}}$).
• Saturation slope. Compare it at low and high $V_{\mathrm{GS}}$. Channel-length modulation gives a slope proportional to $I_{\mathrm{D}}$. DIBL adds a component that is largest near threshold, where a $V_{\mathrm{T}}$ shift matters most.

In simulation the same sweeps run against the PDK’s compact model. The ngspice deck below uses Level 1 with Harris’s 0.6 µm parameters, which reproduces his 2.2 mA top curve.¹ Swapping the .model line for a PDK’s BSIM model, and the M line for the kit’s device, turns it into a real characterization run.

* NMOS output characteristics, square-law (Level 1) model
.model nch nmos (level=1 vto=0.7 kp=120u lambda=0)
M1 d g 0 0 nch W=1.2u L=0.6u
Vd d 0 0
Vg g 0 0
.dc Vd 0 5 0.05 Vg 0 5 1
.control
run
plot -i(Vd)
.endc
.end

Two models of one generic NMOS ($V_{\mathrm{DD}} = 1\,\mathrm{V}$, $V_{\mathrm{T0}} = 0.35\,\mathrm{V}$, currents per µm):

• the square law;
• an $\alpha$-power law ($\alpha = 1.3$) with $\lambda = 0.15\,\mathrm{V}^{-1}$ and DIBL of 80 mV/V, matched to the square law at $V_{\mathrm{GS}} - V_{\mathrm{T}} = 0.3\,\mathrm{V}$.

Both use a smooth subthreshold tail with $n = 1.4$. Switch to the log $I_{\mathrm{D}}$–$V_{\mathrm{GS}}$ view to read $S$. The dotted curve at $V_{\mathrm{DS}} = 0.05\,\mathrm{V}$ shows the DIBL shift. The readouts give $g_{\mathrm{m}}$, $r_{\mathrm{o}}$ (infinite in long-channel saturation), $I_{\mathrm{on}}/I_{\mathrm{off}}$ and $S$.

The SKY130 device tables give model values against e-test specifications, across TT/FF/SS/FS/SF corners, for the 1.8 V FETs. The models are valid for $|V_{\mathrm{GS}}|, |V_{\mathrm{DS}}| \le 1.95\,\mathrm{V}$.⁹

SKY130 NMOS 7/0.15 Idsat (TT / FF / SS)

3.51 / 3.95 / 3.08 mA

SKY130 NMOS Vt, 7/8 vs 7/0.15 (TT)

0.538 vs 0.645 V

α-power exponent, 65 nm (Harris)

≈ 1.3

Typical subthreshold slope at room temperature

≈ 100 mV/dec

Values from the SKY130 device tables.⁹ Readings worth making:

• Corner spread. FF to SS spans 3.95 to 3.08 mA, about ±12% around TT. Timing signoff has to cover that whole spread.
• $V_{\mathrm{T}}$ versus $L$. The short device has a higher threshold than the long one (0.645 vs. 0.538 V). That matches what Harris calls the reverse short-channel effect.²
• Threshold flavors. The LVT device trades 34 mV of $V_{\mathrm{T}}$ for 14% more $I_{\mathrm{dsat}}$. At a typical 100 mV/decade, 34 mV is worth roughly 2× in subthreshold leakage. The tables report leakage too, in log amps.
• NMOS/PMOS ratio. $3.512/1.347 = 2.6$ at equal size, consistent with the 2–3× mobility ratio.¹

For physical scale, at $L = 0.15\,\mu\mathrm{m}$ and $V_{\mathrm{DS}} = 1.8\,\mathrm{V}$ the average lateral field is 120 kV/cm. $\mu E$ with any plausible channel mobility then exceeds the electron $v_{\mathrm{sat}}$ of $10^7\,\mathrm{cm/s}$, so these devices sit well inside the partly velocity-saturated regime the $\alpha$-power law describes.²

The trade space

• $V_{\mathrm{T}}$ selection. $I_{\mathrm{on}} \propto (V_{\mathrm{DD}} - V_{\mathrm{T}})^{\alpha}$, while $I_{\mathrm{off}} \propto 10^{-V_{\mathrm{T}}/S}$. Near $V_{\mathrm{DD}} - V_{\mathrm{T}} \approx 0.4\text{–}0.6\,\mathrm{V}$, a 100 mV $V_{\mathrm{T}}$ cut buys roughly 20–35% drive ($\alpha \approx 1.3$) for 10× leakage at $S \approx 100\,\mathrm{mV/dec}$. Multi-$V_{\mathrm{T}}$ libraries let synthesis spend leakage only on critical paths. SKY130 ships LVT and HVT variants alongside the standard devices.⁹
• $V_{\mathrm{DD}}$ scaling. Because $I_{\mathrm{on}}$ grows only as about $V_{\mathrm{DD}}^{\alpha}$ rather than $V_{\mathrm{DD}}^2$, raising the supply shortens gate delay ($\propto C V_{\mathrm{DD}}/I_{\mathrm{on}}$) less than the square law suggests, while switching energy still grows as $V_{\mathrm{DD}}^2$. The speed bought per unit of power falls faster than a square-law estimate predicts.²
• Channel length. Below the length where velocity saturation dominates, $I_{\mathrm{on}}$ stops scaling as $1/L$. Meanwhile $\lambda$, DIBL and $V_{\mathrm{T}}$ sensitivity to $L$ all get worse. Intrinsic gain $g_{\mathrm{m}} r_{\mathrm{o}}$ falls, which is why analog blocks use longer devices than logic. Gate control over the channel is the lever that the Shrinking chapter’s FinFET and GAA structures pull.
• Temperature. $I_{\mathrm{on}}$ falls with $T$ (mobility), but $I_{\mathrm{off}}$ rises (lower $V_{\mathrm{T}}$, larger $kT/q$). Corner selection reflects this: Harris’s table puts the cycle-time corner at SS/low $V_{\mathrm{DD}}$/high $T$ and the leakage corner at fast devices, high $V_{\mathrm{DD}}$ and high temperature.²

Failure modes

• Hand models outside their range. Sakurai and Newton’s motivating example: with velocity saturation, an 8-input NAND is only about 4–5× slower than an inverter (fast input, large load), while the Shockley model always predicts more than 8×. The series stack shares $V_{\mathrm{DS}}$ and $V_{\mathrm{GS}}$, which relieves velocity saturation in each device.⁶ Use the square law for intuition, never for sizing.
• Extrapolating fitted parameters. $\alpha$-power and similar fits hold only near the $L$, $V_{\mathrm{DD}}$ and corner they were extracted at. Sakurai and Newton note that a parameter set is valid only for a narrow range of channel length.⁶
• Ignoring DIBL in leakage budgets. $I_{\mathrm{off}}$ must be read at $V_{\mathrm{DS}} = V_{\mathrm{DD}}$, not from a low-$V_{\mathrm{DS}}$ transfer curve. The gap is $10^{\eta V_{\mathrm{DD}}/S}$, often several times.
• Threshold apples and oranges. $V_{\mathrm{T,lin}}$ from linear extrapolation, $V_{\mathrm{T,sat}}$ from constant current at high $V_{\mathrm{DS}}$, and a SPICE model’s VTH0 parameter are different quantities. On one 0.18 µm process, linear extrapolation and the $g_{\mathrm{m}}/I_{\mathrm{D}}$ method differed by roughly 20–40 mV.⁸

From hand models to compact models

Circuit simulators need $I_{\mathrm{D}}$, terminal charges and their derivatives at every bias, in every region, evaluated millions of times per transient. The ladder of models trades simplicity for accuracy.

1. SPICE Level 1 (Shockley). The three-region square law with an optional $\lambda$. Sakurai and Newton showed it is “far from accurate in the short-channel region” and insufficient even for first-order relative delay.⁶
2. Power-law and unified hand models. Sakurai and Newton’s nth-power model uses a handful of appearance-oriented parameters. It evaluated in about a third of the time of SPICE Level 3, and its parameters come from a few points on measured curves.⁶ The unified model taught in digital IC courses takes $V_{\mathrm{min}} = \min(V_{\mathrm{GT}}, V_{\mathrm{DS}}, V_{\mathrm{DSAT}})$ and $I_{\mathrm{D}} = k\,(V_{\mathrm{GT}} V_{\mathrm{min}} - V_{\mathrm{min}}^2/2)(1 + \lambda V_{\mathrm{DS}})$, so one expression covers linear, saturation and velocity saturation.⁵
3. Physics-based compact models. BSIM4 extends BSIM3 into the sub-100 nm regime. It has been used from 0.13 µm down to 22/20 nm, and its development is coordinated through the Compact Model Coalition.¹⁰ BSIM-CMG covers FinFETs and other multi-gate devices with a surface-potential formulation; its CMC standard releases date back to 2012.¹¹ Models such as BSIM3, BSIM4 and PSP run to more than ten thousand lines of C.⁵

One equation across all regions

Piecewise models have kinks at region boundaries. The unified model’s min() has a discontinuous derivative at $V_{\mathrm{DSAT}}$, and Level 1 has no current at all below $V_{\mathrm{T}}$. Newton–Raphson in a circuit simulator needs smooth currents and conductances, and leakage analysis needs the subthreshold tail. So production models use single expressions that blend weak and strong inversion. Charge-based all-region models, such as the ACM model used by Schneider and colleagues, are one approach.⁸

The simulation on this page uses the same idea in miniature. It replaces the overdrive with a softplus that becomes exponential below threshold:

φt   = kT/q = 25.85 mV        n = 1.4        Vt = 0.35 V − η·VDS
w    = α · n · φt
VGT* = w · ln(1 + exp((VGS − Vt)/w))           (softplus overdrive)
Isat = K · VGT*^α
Vsat = sqrt( (Pv · VGT*^(α/2))² + (2φt)² )
x    = min(VDS / Vsat, 1)
ID   = Isat · (2 − x) · x · (1 + λ·VDS)

long:  α = 2,   K = 2442 µA/V²/µm, Pv = 1,    λ = 0,     η = 0
short: α = 1.3, K = 1051,          Pv = 0.46, λ = 0.15/V, η = 0.08 V/V

Extracting parameters from measured curves

Fitting a model means choosing parameters so the model’s curves pass through measured ones. Sakurai and Newton made this nearly closed-form.⁶

1. Pick a handful of points on the measured I-V curves.
2. Divide out the channel-length-modulation factor from the saturation points, then solve one equation for the threshold by bisection (convergence within about 10 iterations).
3. Get $n$ and $B$ from the ratio of two saturation currents.
4. Get $K$ and $m$ from two linear-region points.

The whole fit runs in under a second, with no multi-parameter optimizer. The parameters are valid only near the channel length they came from, so a design uses two or three sets.⁶ Full BSIM extraction applies the same idea at much larger scale, fitting many more parameters to sweeps across geometry, bias and temperature.

Defining and extracting the threshold

Because $I_{\mathrm{D}}(V_{\mathrm{GS}})$ is smooth, $V_{\mathrm{T}}$ is defined by a procedure. Most methods use a transfer curve at low $V_{\mathrm{DS}}$ (below $2kT/q$ in Schneider et al.’s analysis).⁸

• ELR (extrapolation in the linear region). Fit a tangent at the point of maximum $g_{\mathrm{m}}$ and take its $V_{\mathrm{GS}}$ intercept. Simple, but biased by mobility degradation, series resistance and the nonlinear charge–voltage relation.
• Transconductance change / second derivative. The peak of $dg_{\mathrm{m}}/dV_{\mathrm{GS}}$. Physically meaningful, but the second derivative of measured data is very noisy.
• Constant current. The $V_{\mathrm{GS}}$ at which $I_{\mathrm{D}} L/W$ reaches a chosen value. Simple and accurate, provided the effective $W$ and $L$ are known.
• $g_{\mathrm{m}}/I_{\mathrm{D}}$. The $V_{\mathrm{GS}}$ where $g_{\mathrm{m}}/I_{\mathrm{D}}$ falls to half its subthreshold peak.

On 0.18 µm devices, these methods spread over about 25–45 mV at each channel length. The $g_{\mathrm{m}}/I_{\mathrm{D}}$ and second-derivative results differ systematically by about $1.2\,n\phi_{\mathrm{t}}$, which is at least 30 mV.⁸ A PDK’s quoted $V_{\mathrm{T}}$ is therefore always tied to a method and a bias. SKY130’s table, for instance, lists separate e-test parameters for each geometry.⁹

The next chapter, Speed and power, turns $I_{\mathrm{on}}$, $I_{\mathrm{off}}$ and the $\alpha$-power law into delay and power. The cell-library chapter shows how these device curves become the timing tables synthesis and place-and-route read.