Guide 2 of 4 · 13 stages

Design Flow

Making a chip is like a relay race. Each team takes the last team’s work, adds detail, and checks that nothing broke. Start anywhere; each chapter stands on its own.

The front end turns a written specification into a checked design made of logic gates. The back end turns that design into a physical layout that meets its speed, power and manufacturing rules.

In practice the stages overlap and loop: synthesis pulls placement information forward, and signoff findings flow back as late fixes. The order here is the dependency order, not a waterfall.

The Expert level assumes you know a chip is described in code, turned into logic gates and then laid out, and not much more.

  1. Front end · what the chip does

    01Specification
    Write down what the chip must do, how fast it must be, how much power it may use and what it may cost. Every later step is checked against this list.
    The team writes down measurable targets for speed, power, size and cost, along with the standard connections the chip must support and the factory process it will use. Every later stage, including testing, is checked against these numbers.
    Performance, power, area and cost targets; interface standards and how compliance will be shown; power and thermal limits; package and I/O; process choice; manufacturing-test, safety and security requirements; and schedule. Mistakes here cost the most later, so good specs are versioned and every requirement links to the test that proves it.
    The targetsFull chapter
  2. 02Architecture
    Sketch the chip’s big parts, such as the parts that do math, the memory and the roads between them, and decide how they work together.
    Architects split the chip into blocks (processors, special-purpose accelerators, memories, the connections between them, and I/O) and decide how memory, clocks and power are organized. Software models test the plan before any hardware is designed.
    Performance modeling, microarchitecture trade-offs, interconnect and NoC topology, memory hierarchy and bandwidth, clock and power domain strategy, IP make-or-buy, partitioning with the floorplan in mind, and early power and area estimates.
    The block diagramFull chapter
  3. 03RTL design
    Engineers write what the chip should do as code. Unlike an app, this code describes circuits that all run at the same time.
    Engineers write register-transfer level (RTL) code, in a language such as SystemVerilog, saying what each register (a group of one-bit memories) holds after every clock tick and what logic computes it. Automatic checks catch common mistakes early.
    Code that simulates and synthesizes the same way, reset strategy, safe crossings between clock and reset domains (CDC and RDC), lint and CDC sign-off, and power intent (UPF) alongside the RTL. Generators such as Chisel and high-level synthesis produce RTL for some blocks.
    The behavior, as codeFull chapter
  4. 04Verification
    Before anything is built, teams test the design on a computer to find mistakes. A mistake found after the chip is made can cost millions of dollars.
    Engineers run the design in simulation under automated test programs, measure which situations the tests have reached, prove the trickiest rules mathematically, and run long software tests on special hardware. It often takes as much effort as writing the design, or more.
    Coverage-driven constrained-random verification, formal property checking, emulation and FPGA prototyping for software bring-up, power-aware and gate-level simulation, and the coverage criteria that define done.
    ConfidenceFull chapter
  5. 05Logic synthesis
    Software turns the code into a parts list: thousands of small, ready-made circuit pieces and the wires between them.
    A synthesis tool turns the design code into a netlist: a list of ready-made circuit blocks from a library, called standard cells, and the wires between them, chosen to meet a speed target while keeping area and power low.
    Elaboration, technology-independent optimization, technology mapping, timing-driven sizing and restructuring, clock gating, retiming, physical-aware synthesis, and equivalence checking against the RTL.
    The gate netlistFull chapter
  6. 06Design for test
    Add hidden test circuits, so every chip made at the factory can be checked for flaws.
    The chip’s one-bit memory cells are linked into test chains, memories get small built-in testers, and software works out the test patterns that reveal manufacturing defects.
    Scan insertion and compression, test-pattern generation (ATPG) for stuck-at, transition and cell-aware fault models, memory and logic self-test, JTAG boundary scan, test-mode timing, and test cost against coverage.
    Test accessFull chapter

  7. Back end · where everything goes

    07Floorplanning
    Decide where the big pieces go on the chip, like planning the rooms before building a house.
    Decide how big the chip is, where its connections to the outside world sit, and where large ready-made blocks such as memories go, leaving room and wiring lanes for the millions of small cells placed later.
    Die and core sizing from utilization targets, macro placement and orientation, pin assignment, channels and halos, hierarchical partitioning, voltage areas for power domains, and early congestion and timing feasibility.
    The die outlineFull chapter
  8. 08Power planning
    Build the chip’s power wiring, so every part gets a steady supply of electricity.
    A mesh of power wires on the chip’s metal layers carries the supply to every cell. The goals: lose little voltage on the way (IR drop) and keep the wires from wearing out (electromigration).
    PDN topology and strap pitch on upper metals, via arrays, power switches for gated domains, static and dynamic IR analysis, EM limits, decap insertion, and backside power delivery at the newest nodes.
    The power gridFull chapter
  9. 09Placement
    Software finds a spot for each of hundreds of thousands of tiny parts, keeping connected parts close together.
    Software gives each prebuilt logic cell an exact spot in neat rows, keeping connected cells close so wires stay short and signals arrive in time, without crowding any area. It works in three passes: rough, snap into rows, then polish.
    How global placement trades wirelength against density (electrostatic models), then legalization and detailed placement, with timing- and congestion-driven passes and buffering, gate sizing and threshold-voltage swaps along the way.
    The cell layerFull chapter
  10. 10Clock tree synthesis
    The clock is the chip’s heartbeat, a signal that ticks millions or billions of times a second. This step delivers each tick everywhere at almost the same moment.
    CTS builds a branching network of small amplifiers that carries the clock signal to every flip-flop, so each gets the tick at nearly the same moment and with a sharp edge. Timing is then re-checked with the real clock delays.
    Skew groups, useful skew, non-default rules and shielding, multi-source and mesh topologies, clock gating, OCV and CPPR, and post-CTS hold fixing.
    The clock networkFull chapter
  11. 11Routing
    Draw the real wires between all the parts. They are stacked in many layers, like floors in a parking garage.
    Turn every connection into metal: global routing plans rough paths across a coarse grid, then detailed routing draws the exact wires and the vias between layers, obeying the factory’s design rules.
    Track assignment, timing- and crosstalk-driven routing, via optimization, DRC convergence, antenna fixing, and multi-patterning-aware routing at advanced nodes.
    The metal stackFull chapter
  12. 12Signoff
    Run the final checks that prove the chip will be fast enough, can be made and matches the design.
    The last checks on the finished layout: signals arrive on time in every condition, every shape can be manufactured, the drawing matches the intended circuit, and the power wiring holds up.
    Timing in every mode and corner on extracted wire parasitics, with variation margins and crosstalk; DRC, LVS and the other physical checks; IR drop and electromigration; and the ECO loop that fixes what’s left.
    Proof it worksFull chapter
  13. 13GDS & tapeout
    Save the finished design as one file and send it to the factory that will make the chip.
    The finished layout gets its last pieces, including dummy metal fill, and is saved as one file in GDSII or OASIS format. Sending that file to the foundry, the chip factory, is called tapeout.
    Merging real cell layouts over their abstracts, metal fill and density rules, final DRC and LVS on the merged file, and the tapeout checklist. Then the foundry’s mask data preparation, including optical proximity correction.
    The mask dataFull chapter