Signoff

Signoff is the final verification of the routed layout before tapeout, in four families: timing (including crosstalk), physical verification against the foundry’s rules, power integrity, and logical equivalence. What sets it apart from the checks run during implementation is accuracy. Every earlier stage uses simplified models so it can run quickly and iterate. Signoff replaces each simplification with the most accurate model the schedule allows:

• Wires: estimated lengths become resistance and capacitance extracted from the routed geometry, once per manufacturing extreme of the metal.
• Power: an ideal supply at every cell becomes a solved model of the power grid that shows where the voltage sags.
• Conditions: a few corners become the full set of scenarios, each pairing a way the chip is used (a mode) with a combination of process, voltage and temperature (a corner).
• Variation: a flat safety margin becomes per-cell statistical variation.
• Rules: “the router followed the rules” becomes a full run of the foundry’s own rule files on the final merged layout file (GDSII or OASIS).

The placer and router contain their own timers, and they never agree exactly with the signoff timer. When they disagree, the signoff number wins.

The scope keeps growing. Device and interconnect corners multiply: three device corners, five interconnect corners, two temperatures and two voltages already make 60 combinations, and signoff at 40 and 28 nm meant hundreds of mode-corner combinations.¹¹ Checking only corners is both pessimistic at the corners it checks and risky at the ones it skips, which is the argument for statistical methods.⁹ Path-based timing, the more exact mode used to close the last violations by re-timing each failing path with its own conditions, costs four times the runtime or more.⁸ So most of the engineering is judgment: choosing which scenarios matter, which pessimism is safe to remove, and which violations are real.

Two details cause most input problems.

Parasitic annotation. “Annotation” means attaching each net’s extracted values to that net in the timer. Several choices hide in that step. OpenSTA’s read_spef, for example, can keep coupling capacitors as connections between two nets (needed for crosstalk analysis) or tie them to ground with a multiplying factor; accepts separate min and max SPEFs per scenario; stitches SPEFs from separately extracted blocks together at the block boundaries; and ignores some SPEF fields (it uses the library’s pin capacitances instead of the SPEF’s *I values). If a net is missing from the SPEF, the timer quietly falls back to an estimate, and the path looks fine. So every run includes report_parasitic_annotation, which lists unannotated nets.²

Version control of foundry data. The rule deck, the extraction technology file and the Liberty set are all versioned by the foundry, and an update can turn a clean layout dirty. The checklist records exactly which versions were run.

The checks, in the order they run

1. Extraction. The extractor reads the routed layout and computes, for every net, a resistor network, its capacitance to ground and its coupling capacitance to each neighbor, using a calibrated technology file generated once per process and per interconnect (RC) corner, and writes the results as SPEF.⁴
2. Static timing. The timer reads the gate-level netlist, one Liberty library per process-voltage-temperature corner, the SPEFs and one SDC constraint file per mode. For every pin it computes when signals arrive and when they are required, then checks setup and hold on every timing path, recovery and removal on asynchronous reset pins, the library’s limits on slew, capacitance and fanout, clock-gating checks and minimum pulse widths.²
3. Signal integrity. The coupling capacitances let switching neighbors change a net’s delay or put a glitch on it. SI-aware timing adds both.
4. Physical verification. DRC, LVS, ERC, antenna and density checks run on the final merged layout with the foundry’s rule deck.¹⁴
5. Power integrity. The power grid is solved for static and dynamic IR drop, and wire currents are checked against electromigration limits.
6. Equivalence. Logical equivalence checking (LEC) proves the final netlist matches the post-synthesis netlist.
7. Fix and repeat. Violations become ECOs, and every ECO round reruns all of the above on what changed.

The sections below take each in turn and explain where the difficulty lies.

Corners, modes and dominance

A device corner is named for how fast the factory made the two transistor types, NMOS and PMOS: slow-slow, typical, fast-fast, and the skewed slow-fast and fast-slow. An interconnect corner is a manufacturing extreme of the metal. Cworst is wires printed wide and thick, so close to their neighbors that capacitance is maximal; RCworst is wires printed narrow and thin, so resistance rises and the product of resistance and capacitance is maximal. A process may define 3 to 6 device corners and 5 to 11 interconnect corners before voltage and temperature. Every independent supply domain multiplies the set: one engineer quoted in an industry article puts a typical design with two power supplies at 30 or more corners.⁶

Nobody signs off the raw cross product. Step by step, teams:

1. Pair device and RC corners in the direction that hurts: slow devices with maximum RC, fast devices with minimum RC.⁶ The first pairing targets setup, the second hold.
2. Add the cross pairings that catch different net types. A short net’s delay is mostly its driver charging capacitance, so it is worst at Cworst; a long net’s resistance matters, so it can be worst at RCworst.
3. Run a dominance analysis: a scenario dominates if it sets the worst slack for at least one endpoint (the flip-flop input or chip output where a path ends). Scenarios that never do are dropped.

Each mode brings its own SDC. In scan-shift mode, for example, test data is shifted through long chains of flip-flops on a slow test clock; the paths are short flop-to-flop hops, so hold matters more than in functional mode. Low-power modes change which supplies, and so which libraries, apply. OpenSTA expresses this directly: read_sdc -mode loads a mode’s constraints, and define_scene binds a mode to Liberty files and named min and max SPEFs.²

Variation models and pessimism

Every margin for variation costs slack, so the question is how much margin is honest. The methods, in the order flows adopted them:

• Flat OCV. Multiply late paths by one global derate such as 1.05 and early paths by 0.95, whatever the cell, slew or load. Simple, but the excess pessimism led to over-design and real performance limits.⁷
• AOCV. Look the derate up by path depth (the number of stages) and by distance across the die, which accounts for random variation cancelling out along deeper paths and reduces the pessimism of one global value.⁷
• POCV with LVF. Model each cell’s local variation as a function of its own delay and load. The variation (a sigma, or standard deviation) is characterized by Monte Carlo circuit simulation at each slew and load point and stored in the library in Liberty Variation Format (LVF).⁷ The timer then treats each stage’s delay as a mean plus a spread and combines the spreads statistically along the path.

A worked example of why statistics helps: ten stages, each with a sigma of 1 ps. A 3-sigma margin applied stage by stage adds $10 \times 3 \times 1 = 30\,\mathrm{ps}$. If the stages vary independently, their sigmas combine by root-sum-square instead: $\sqrt{10} \times 1 \approx 3.2\,\mathrm{ps}$ for the path, so a 3-sigma margin of about 9.5 ps. Random variation on long paths largely cancels.

Two more sources of pessimism stay under the engineer’s control. CPPR must be on for every check: when the launch and capture clocks share a stretch of clock tree, derating that stretch late for one and early for the other counts a physically impossible difference, and CPPR credits back the shared delay × (late derate − early derate). The other is the choice between graph-based and path-based analysis. Graph-based analysis keeps one worst arrival and slew per pin; at a gate with several inputs, the output inherits the worst input’s slew even for a path that enters through a sharper one. Path-based analysis re-times a single path with its own slews. On one published 28 nm design signed off at a 1.2 ns clock period, graph-based analysis was up to 110 ps more pessimistic than path-based on an endpoint, and path-based cost 4× or more in runtime. The usual compromise is graph-based everywhere and path-based on at least the paths that fail graph-based, to avoid fixing paths that aren’t really failing.⁸

Signal integrity in practice

Crosstalk analysis has a circular dependency. A net’s timing window is the interval in which it can switch. An aggressor only changes a victim’s delay if their windows overlap, and the size of the change depends on how they align; but the windows depend on delays, including the crosstalk delays being computed. Tools break the circle by iterating: compute windows, compute delta delays, update windows, and repeat until nothing changes.¹⁰ The worst alignment is the one that delays the signal at the victim’s receiver the most, not the one that maximizes the victim stage’s own delay. Current-source driver models handle that better than the classic slew-and-load lookup tables, because they don’t assume ramp-shaped inputs or a single lumped load capacitor.¹⁰

In practice crosstalk shows up after routing as new setup failures on long parallel runs, and new hold failures where an aggressor speeds up a short path. The basic fix is a routing ECO that moves neighboring wires away from the critical net.³ Glitch noise is checked separately: a glitch on a quiet net must stay too small to cross the switching threshold of the gates it reaches.¹

Physical verification at scale

Rule decks no longer consist of simple width and spacing checks. Advanced processes add many contextual rules, where the allowed value depends on the surroundings (for example, a larger spacing next to a wide wire, or extra enclosure where a wire ends). These rules drive up run time and push tools to cut the layout into tiles and exploit its hierarchy to run in parallel.²¹ Signoff DRC runs on the final merged layout file with fill and all third-party blocks included, because a rule can fail at the boundary between two blocks that are each clean on their own.

For LVS of a digital block, the reference is a SPICE (or CDL, a SPICE dialect) netlist built from the final gate-level Verilog plus each cell’s transistor netlist. Large designs are compared hierarchically rather than flattened into one huge transistor list; the open-source Netgen, for example, supports hierarchical LVS.¹⁹ Check power and ground connectivity first: an unconnected well tap or a missing supply label on a large block fails LVS as surely as a signal short. Antenna violations are fixed with protection diodes or a jump to a higher layer near the gate.¹⁴ After any metal-only change, an XOR of the old and new layouts (a geometric comparison that shows only the shapes that differ) confirms that only the intended shapes moved.¹⁴

Power integrity and timing interact

Dynamic IR drop is the dip in supply voltage caused by local demand and switching patterns, and it has to be bounded for the circuit to meet timing.²⁵ The two ways to analyze it trade off. Vector-based analysis replays switching activity from simulation, but a large chip needs many patterns to cover its behavior and good patterns arrive late in the project. Vectorless analysis assigns switching statistically, so it is faster and available earlier, but harder to make accurate. Run time is significant: in one study, a commercial tool spent about 2.5 hours on the dynamic analysis of a design with about two million cells, and more than four hours in total.²⁵

The drop then has to be fed back into timing. The usual approach is a budget: power integrity work keeps the drop below a specified limit, and timing is signed off with cell delays at a worst-case voltage corner that assumes that limit. But the real grid never meets the limit exactly, so some cells see more drop than budgeted and slow down. The more exact approach annotates each cell with its own simulated supply voltage, re-times, and fixes the paths that fail, for example by resizing cells in an ECO.²⁶ On the grid side, the fixes are a stronger grid (wider stripes, more vias) and decoupling capacitors: decap cells, which store charge right next to busy logic, inserted where the drop is highest.²²

Electromigration

EM checks today are mostly rule-based. Step by step: estimate each wire’s current density; flag wires above a limit derived from Black’s equation, a semi-empirical formula for a wire’s mean time to failure as a function of current density and temperature; then use the Blech criterion to clear short wires. Migrating atoms pile up at one end of a wire and the resulting mechanical stress pushes back against them; if the product of current density and wire length stays below a technology-specific value, the two balance and the wire is effectively immortal. A widely used variant simply gives wires below a threshold length a higher current limit.²⁷ Power-grid wires carry mostly one-way (DC) current. Signal and clock wires carry current that reverses each transition, which partly undoes the damage, so they are checked with an effective current density instead.²⁷

ECO discipline

Late ECOs are limited by what can still change. Once placement is frozen, a functional patch must be mapped onto nearby spare cells. Too few spares, or long wires to reach them, create new timing and congestion problems, so patch generation itself should take spare locations into account.²⁸ Timing ECOs come from the signoff timer, which sees every scenario, and go back to the routing tool as sizing and buffering changes. Every round ends with re-extraction, the full scenario set, physical verification and LEC. Teams track violation counts per check per round: a flat or rising count means the fixes are fighting each other across scenarios.

The checklist

A typical tapeout checklist requires:

• zero setup, hold, recovery/removal and max-transition violations in every signed scenario, with path-based analysis on any remaining marginal endpoints;
• crosstalk delta delay included and glitch analysis clean;
• DRC, LVS, ERC, antenna and density clean with the current foundry deck, plus approved waivers;
• static and dynamic IR drop within budget;
• EM clean at the target lifetime and temperature;
• LEC passing;
• the exact tool, deck, library and SPEF versions recorded.

The report is in OpenSTA’s format. Check the arithmetic yourself. OCV multiplies the launch clock latency (0.412) and the data path (0.564 from the launch flop’s clock pin to the capture flop’s D pin) by 1.05, and the capture clock latency (0.398) by 0.95. Arrival: $0.4326 + 0.5922 = 1.0248$. Required: $0.800 + 0.3781 - 0.050 - 0.074 = 1.0541$. Slack: +0.029. The two clock paths share 0.220 ns of tree before they split, so CPPR credits $0.220 \times (1.05 - 0.95) = 0.022\,\mathrm{ns}$, restoring +0.051. At 0.75 ns the CPPR credit alone separates +0.001 ns from −0.021 ns: once variation is on, removing double-counted pessimism decides pass or fail. Before signing such a path off, ask two questions: what path-based analysis would report, and whether the library’s setup time carries its own variation margin (from LVF) too.

The Expert view shows each rule as a line of a KLayout-style deck. Sort the checks into three kinds: single-layer edge checks (width and spacing), two-layer checks (enclosure of V1 by M1) and polygon measurements (area). Then think about how each is computed: spacing and enclosure as queries for pairs of edges closer than a distance, area per merged polygon. That split is the basis of the sweepline algorithm in Under the hood.

Three artifacts from late signoff, all illustrative. First, the physical verification summary after a round of ECOs. The layout is in OASIS format (.oas), and the LVS reference is a CDL netlist.

==== Physical verification summary (illustrative) ====
Layout: top_final.oas    Netlist: top_final.cdl    Deck: generic_10M rev 1.4

DRC   rules run: 4,812   rules violated: 3   results: 7
  M2.S.3    M2 space to wide M2 (width > 0.300) >= 0.080        4
  V3.EN.2   M3 end-of-line enclosure of V3 >= 0.030             2
  M7.DEN.1  M7 density per 50 um window >= 20%                  1
ANT   rules run: 10      violations: 0
ERC   floating gates: 0   wells without tap: 0   supply shorts: 0

LVS   result: INCORRECT
              layout      schematic
  instances   1,284,551   1,284,551
  nets        1,302,117   1,302,118
  ports       412         412
  mismatched nets: 2
    u_lsu/n_4471 + u_lsu/n_4472  ->  one layout net (short)
    short path: M3 (812.40, 1204.66) - V3 - M4 (812.40, 1204.70)

Second, the power integrity summary for the worst functional scenario. Javg and Jrms are the average and root-mean-square current densities that EM limits are written in.

==== Power integrity summary (illustrative) ====
Scene: func_ss_0p72v_125c   VDD nominal 0.720 V   PDN: M1-M10 + bumps

STATIC (average current per cycle)
  Total VDD current           2.41 A
  Worst IR drop VDD+VSS       14.2 mV  (2.0%)   u_core/u_alu region

DYNAMIC, vectorless (data toggle 0.20, clock 1.0, 1.25 ns window)
  Worst effective drop        68.4 mV  (9.5%)   u_core/u_mul/U8812
  Instances above 8% budget   1,906
DYNAMIC, vector-based (VCD 18.40-18.65 us, mul_burst test)
  Worst effective drop        52.7 mV  (7.3%)   u_core/u_mul/U9034

EM (125 C, 10-year target)
  Power grid: 3 segments over Javg limit   M2 rail at (1410.2, 655.0)
  Signal: 1 net over Jrms limit            clk_core trunk, M8
  Via arrays: 0 over limit

Third, ECOs. The signoff timer can try fixes in place, with every scenario loaded, before handing them to the routing tool. These are OpenSTA netlist-edit commands; real flows replay the same edits in the place-and-route tool, then re-extract.²

# eco_fix.tcl  (illustrative; OpenSTA netlist-edit commands)
# Timing ECO: upsize a driver on a failing setup path
replace_cell u_core/u_lsu/U78 NOR2_X2

# Hold ECO: insert a delay cell in front of a capture pin
make_net u_core/eco_n1
make_instance u_core/eco_hold1 DLY_X1
disconnect_pin u_core/n_2291 {u_core/u_lsu/addr_reg[3]/D}
connect_pin u_core/n_2291 u_core/eco_hold1/A
connect_pin u_core/eco_n1 u_core/eco_hold1/Z
connect_pin u_core/eco_n1 {u_core/u_lsu/addr_reg[3]/D}

# Metal-only functional ECO: use a pre-placed spare NAND2
disconnect_pin u_core/spare_tielo u_core/spare_nand2_17/A1
disconnect_pin u_core/spare_tielo u_core/spare_nand2_17/A2
disconnect_pin u_core/n_771 u_core/u_dec/U12/A1
connect_pin u_core/n_771 u_core/spare_nand2_17/A1
connect_pin u_core/n_772 u_core/spare_nand2_17/A2
make_net u_core/eco_n2
connect_pin u_core/eco_n2 u_core/spare_nand2_17/ZN
connect_pin u_core/eco_n2 u_core/u_dec/U12/A1

report_checks -path_delay min_max -through {u_core/u_lsu/addr_reg[3]/D} -digits 3
write_verilog results/top_eco1.v

• Corner pruning that drops the dominant scenario. A scenario pruned early because it never set the worst slack can become the worst one after an ECO changes which paths are critical. Re-run the dominance analysis after large ECO rounds.
• Pessimism removal used as a fix. Path-based analysis and POCV are legitimate, but hundreds of endpoints passing by a few picoseconds only after path-based re-timing are still a yield risk. Track how much slack came from removing pessimism and how much from real fixes.
• Correlation gaps. The place-and-route tool’s built-in timer and the signoff timer disagree, so the optimizer works on the wrong paths. Compare the two on a sample of endpoints and adjust the implementation flow’s margins until they agree.
• IR drop left out of timing. A path with positive slack at nominal voltage fails inside a hotspot where the supply dips 9%. Either budget the drop in the timing run or re-time hotspot paths with their simulated supply.²⁵
• Signal EM on clocks. Like other signal wires, clock wires carry current in both directions and get the signal-wire EM treatment.²⁷ But a clock switches every cycle, far more often than a typical data net, so checking it with the switching rate assumed for data nets understates its current and misses violations.
• Spare cells in the wrong place. A metal-only ECO fails when the nearest suitable spare is far away and the long wire to it breaks timing.²⁸
• Unreviewed waivers. DRC waivers carried over from a previous project or deck version, or reset timing exceptions copied without review, are where bugs escape to silicon.

STA as longest paths on a DAG

Cut the netlist at the flip-flops and the logic between them becomes a directed acyclic graph (DAG): nodes are pins, edges carry cell and wire delays, and no path loops back on itself. Timing is then two passes over that graph:³

1. Forward. Visit nodes in topological order (every node after all of its inputs). Each node’s actual arrival time (AAT) is the maximum, over its fan-ins, of the fan-in’s arrival plus the edge delay.
2. Backward. Visit nodes in reverse order. Each node’s required arrival time (RAT) is the minimum, over its fan-outs, of the fan-out’s required time minus the edge delay.
3. Slack. At every node, $\text{slack} = \mathrm{RAT} - \mathrm{AAT}$. Negative slack anywhere marks a violation.

Both passes touch each edge once, so the work grows linearly with the size of the graph, which is why STA scales to billions of pins where circuit simulation cannot.³ Production timers keep separate rise and fall, early and late values at every node, propagate slews alongside arrivals, and update only the affected part of the graph after an ECO.

Graph-based vs. path-based

Storing one value per node is the source of pessimism. At a gate with several inputs, graph-based analysis propagates the worst input slew to the output even if the reported path enters through a different pin with a sharper slew. A slower slew makes every following stage slower, so the error accumulates along the path and into the capture flop’s setup time. Path-based analysis takes the paths GBA reports and recomputes each with its own slews (and its own depth for AOCV), so its slack is never worse than GBA’s. Enumerating paths is the cost: in Kahng et al.’s measurements PBA ran 4× or more slower, which is why it runs only on violators.⁸

Statistical STA

Visweswariah’s method writes every delay, arrival time and slack in one canonical first-order form: a mean, plus a sensitivity to each global source of variation (each modeled as a unit Gaussian), plus an independent random term. Adding two such quantities is easy: the result is in the same form. Taking their max is not, because the max of two Gaussians isn’t Gaussian. So the method computes the tightness probability (the chance that one arrival is the later one) and the mean and variance of the max, then writes the result back in canonical form with that mean and variance matched. The result is approximate, but the traversal stays linear in circuit size and in the number of variation sources, and every slack comes out with sensitivities that show what makes a path fragile.⁹ POCV, the method signoff flows adopted, is a much simpler statistical model: each cell carries its own characterized variation, stored in the library as LVF tables.⁷ Treating the stages as independent, their sigmas combine by root-sum-square instead of adding linearly, as in the worked example under How it works.

Delay models

The classic library model, NLDM, describes each timing arc as tables of delay and output slew indexed by input slew and a single lumped output capacitance. Two of its assumptions break down at advanced nodes: the input is not a clean ramp, and a resistive wire does not behave like a single capacitor. Current-source models instead describe the driver’s output current as a function of the voltages on its input and output pins, so the tool can compute the actual output waveform, even with a noisy input, into the real wire network. Not assuming ramp inputs or lumped loads is also what makes them a better basis for crosstalk analysis.¹⁰

RC extraction: patterns vs. field solvers

A field solver computes capacitance from Maxwell’s equations on the real 3-D geometry. It is the most accurate method, but far too expensive for the billions of wire segments on a chip. Full-chip extractors instead cut the layout into small geometries and match each against a pattern library. The library is built once per process: enumerate sample geometries, solve each with a field solver, and fit formulas or tables to the results. The 2.5-D variant approximates 3-D effects by combining 2-D cross-sections taken in two directions.⁵ OpenRCX’s Extraction Rules file is this kind of calibration: capacitance and resistance as functions of the distance to the nearest wire and the wiring density above and below.⁴ The weaknesses are pattern coverage, since each new process node adds structures, and table size, which is why researchers are fitting neural-network capacitance models to field-solver data.⁵

LVS as graph matching

LVS has to decide whether two netlists with millions of devices are the same circuit, even though nothing in the layout says which device corresponds to which. The classic Gemini approach:²⁰

1. Model each netlist as a bipartite graph: device vertices on one side, net vertices on the other, an edge for each device terminal. Making nets explicit vertices cuts the edge count for a net with $N$ terminals from $N(N - 1)/2$ to $N$.
2. Give every vertex an initial label from invariants that don’t depend on naming, such as device type and net degree, and group vertices with equal labels into partitions.
3. Refine iteratively: each vertex’s new label combines its old label with its neighbors’ labels. Integer labels stand in for exact ones and give the same result with very high probability.
4. If both graphs refine identically into partitions of one vertex each, the pairing is the match.

Interchangeable terminals, such as a transistor’s source and drain, are grouped into equivalence classes so they don’t cause false mismatches. Symmetric circuits leave partitions that won’t split; the matcher guesses a pairing, keeps relabeling, and backtracks if the guess fails. Memory arrays are the slow case.²⁰ Netgen’s author notes that, as far as he knows, all LVS tools use this same class-partitioning approach.¹⁹ KLayout’s LVS shows the pipeline before the comparison: derive device regions with Boolean layer operations, extract devices, declare which layers connect to which, simplify (merge transistors drawn as several fingers, drop floating nets), then compare against the SPICE reference.¹⁸

DRC as polygon geometry

A DRC engine runs computational-geometry operations on polygons and edges.²¹ Width and space checks return edge pairs, the two edges that violate the distance; Boolean operations derive helper layers (for example “M2 wider than 0.3 µm” for a width-dependent spacing rule); and the engine can work flat, tiled for memory and threads, or hierarchically so a cell checked once covers every instance.¹⁷

The core spacing check is a sweepline problem. For horizontal edges, move a vertical line across the layout from left to right, keeping the edges it currently crosses in a balanced search tree ordered by $y$. When an edge enters, query the tree for edges within the spacing value $\delta$ and report each as a violation. With a heap of event points this runs in $O(n \log n + k)$ time for $n$ edges and $k$ violations, which is optimal. X-Check parallelizes this on GPUs and reports average speedups of 45× on space checks and 61× on enclosing checks against a multi-threaded CPU checker.²¹ Hierarchy is the other lever: a rule that can be decided inside a cell is checked once per cell, and only interactions across cell boundaries need context.

IR drop as a sparse linear system

For DC analysis the power network is a resistor network. Writing Kirchhoff’s current law at every node (nodal analysis) gives $G x = b$, where $G$ is the conductance matrix, $x$ the unknown node voltages and $b$ the cell currents and supply connections.²³ The size is the problem: these systems commonly have $10^6$ to $10^9$ unknowns, heading toward $10^{10}$ for detailed full-chip models.²⁴ And the currents are large: 100 W at 1 V means 100 A, and 100 A through just 1 mΩ already drops 100 mV, 10% of the supply.

Each node connects only to a few neighbors, so $G$ is sparse, and DC power-grid analysis typically gives a symmetric positive-definite matrix. Two solver families exploit that: Cholesky factorization, which factors $G$ once into triangular pieces, and the conjugate gradient method, which converges iteratively without factoring. Power-grid matrices are often badly conditioned (conductances vary over a huge range), so conjugate gradient needs a good preconditioner to converge quickly.²⁴ Dynamic analysis adds capacitance (decap, cell and wire) and gives

Backward Euler with time step $h$ turns each step into²³

The matrix on the left stays fixed for a fixed step, so one factorization serves every time point and only the right-hand side changes. The hard part becomes the currents $b(t)$ themselves: vector-based analysis derives them from simulated switching activity, vectorless analysis from estimated activity.²⁵