Signoff
Beginner
The last set of checks a chip design must pass before it goes to the factory.
Novice
The checks run on the finished layout before it goes to the factory: that signals arrive on time, that every shape follows the factory’s rules, that the drawing matches the intended circuit, and that the power wiring is strong enough. Each check has an owner who approves it.
Expert
The final verification of the routed, filled layout: timing in every scenario on extracted parasitics, physical verification (DRC, LVS, ERC, antenna, density), power integrity (IR drop and electromigration) and equivalence checking. It is run with trusted (“golden”) tools and the foundry’s own rule files, and the deliverable is a checklist in which every remaining exception has a recorded, reviewed reason.
Explained in Signoff (Design Flow).
See also: Static timing analysis (STA), Design rule checking (DRC), Layout versus schematic (LVS).