Layout versus schematic (LVS)
Beginner
Checking that the drawing is exactly the circuit the designers meant.
Novice
Rebuilding the circuit from the layout drawing (which transistors exist and which wires connect them) and comparing it with the circuit the designers intended. It reports shorts (wires touching that shouldn’t), opens (breaks in a wire) and missing or wrong devices.
Expert
Device and connectivity extraction from the layout, then comparison with a reference transistor netlist (SPICE/CDL) built from the final gate-level netlist and each cell’s transistor netlist. Comparison is graph matching by iterative partition refinement, usually hierarchical. Power pins, well ties and missing labels cause many first-run failures.
Explained in Signoff (Design Flow).
See also: Design rule checking (DRC), Electrical rule check (ERC).