Static timing analysis (STA)
Beginner
A way to check that every signal in the chip arrives on time. The chip never has to run.
Novice
A method that adds up the delays of every gate and wire on every path between storage cells and checks that each signal arrives in time for the clock tick. It uses arithmetic on known delays, not test inputs, which is why it is called static.
Expert
Computes, for every pin, the latest and earliest time a signal can arrive and the time it is required, then checks setup, hold and other rules on every path. It runs once per scenario, applies variation margins and removes double-counted margin on shared clock wiring (CPPR), adds crosstalk effects, and can re-time the worst paths individually (path-based analysis) to remove pessimism.
Explained in Signoff (Design Flow).
See also: GBA vs. PBA, MCMM (multi-mode multi-corner).