Transition fault
Beginner
A pretend flaw where a signal still gets to the right value, but too slowly.
Novice
A fault model for timing defects: a wire that is too slow to change from 0 to 1 (slow-to-rise) or from 1 to 0 (slow-to-fall). A test first sets the wire to its old value, then flips it and checks the result at the chip’s full clock speed.
Expert
Models a large delay at one spot. Each test is a stuck-at-style test preceded by an initializing pattern, so it needs two patterns and an at-speed capture. It misses small extra delays on short paths, which is what timing-aware and path delay tests are for.
Explained in Design for test (Design Flow).
See also: Path delay fault, At-speed test.