Glossary

Path delay fault

Beginner

A pretend flaw where each step along a route is a little slow, and together they make the whole route too slow.

Novice

A fault model in which the total delay along one specific chain of gates (a path) is longer than one clock period, even though no single gate is badly slow. Each path has a rising and a falling version.

Expert

Models delay spread along a path. The number of paths grows exponentially with circuit size, so teams test the critical paths that timing analysis reports. A robust test detects the fault whatever the other paths do; a non-robust one assumes they are fault-free.

Explained in Design for test (Design Flow).

See also: Transition fault.

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