At-speed test
Beginner
Testing the chip at its real working speed, to catch flaws that only make signals a bit late.
Novice
A scan test in which a change is started and its result caught exactly one normal clock period apart, so a path that is even slightly too slow gives the wrong answer. Loading and unloading the chains can still run slowly.
Expert
Targets transition, path delay and small-delay faults. Needs closely spaced launch and capture pulses (usually from on-chip clock control), timing signoff in test mode, and care with capture power and supply droop.
Explained in Design for test (Design Flow).
See also: Launch-on-capture (LOC), Launch-on-shift (LOS).