Timing closure
Beginner
The work of tweaking a design until every signal gets where it is going before the next clock tick.
Novice
The loop of checking timing, changing the design, its constraints or the tool settings, and rebuilding, until every path meets the clock (slack of zero or more). On an FPGA it has to be done without changing the chip itself.
Expert
Iterating logic and implementation choices (pipelining, retiming, floorplanning, tool directives, physical optimization) until worst negative slack is zero or positive. On an FPGA the delay model is fixed by the device and its speed grade.
Explained in From hardware code to bitstream (Architectures).
See also: Static timing analysis (STA), Slack, Critical path.