Timing budget
Beginner
How much of its tiny time limit a signal may spend in each piece of a chip, so each team knows its target.
Novice
When a signal must pass through two blocks within one tick of the clock, the share of that time each block may use. Each block’s team gets its share as a target, so it can finish its block without waiting for the other.
Expert
Written into each block’s SDC constraints as input and output delays on its pins, derived from the top-level floorplan’s estimates of wire and buffer delay. Too generous a share on one side starves the other, so budgets are revisited as the blocks mature.
Explained in Floorplanning (Design Flow).
See also: Hierarchical design (partitioning), SDC (timing constraints).