SDC (timing constraints)
Beginner
Instructions that tell the tool how fast the chip must run.
Novice
Synopsys Design Constraints: the file of timing goals, written as short commands. create_clock says how fast the clock ticks; set_input_delay and set_output_delay say how much of each tick is used up outside the block.
Expert
A Tcl-based format that synthesis, timing analysis and layout tools all read. It defines clocks, timing budgets at the block’s inputs and outputs, exceptions (paths to ignore or to give extra cycles), clock margin and design-rule limits. A wrong constraint silently changes what every tool optimizes and checks, so SDC gets its own review.
Explained in Logic synthesis (Design Flow).
See also: Slack, False path, Multicycle path.