False path
Beginner
A route the tool is told to ignore when checking speed, because no signal ever really needs to race along it.
Novice
An SDC command (set_false_path) telling the tools to ignore a path for timing, for example a signal crossing between two unrelated clocks through a synchronizer circuit built for that purpose.
Expert
An exception that removes a path from both optimization and checking. Use it only where a synchronizer or protocol makes timing irrelevant, scope it narrowly and review it: a wrong false path hides a real timing bug until the chip comes back.
Explained in Logic synthesis (Design Flow).
See also: SDC (timing constraints), Multicycle path.