Multicycle path
Beginner
A route that is allowed more than one beat of the chip’s clock to finish.
Novice
An SDC command (set_multicycle_path) that gives a path more than one clock cycle, used when the design only reads the result every few cycles.
Expert
Moves the setup check cycles later. In standard SDC the hold check moves with it, so a setup multiplier of is normally paired with a hold multiplier of to put the hold check back where it was.
Explained in Logic synthesis (Design Flow).
See also: SDC (timing constraints), False path.