Reset domain crossing (RDC)
Beginner
A spot where resetting one part of the chip can scramble a neighboring part that wasn’t reset.
Novice
A path from a flip-flop on one reset signal to a flip-flop on a different reset, or on none. If the first is reset while the second keeps running, the second sees its input jump at an arbitrary moment and can be caught mid-change, even with a single clock.
Expert
Asserting an asynchronous reset is untimed relative to the receiving flop’s clock, so it behaves like a clock crossing. The fixes: order the resets so the receiver enters reset first, isolate the receiver with an enable while the source is in reset, or put both on the same reset.
Explained in RTL design (Design Flow).
See also: Reset synchronizer, Clock domain crossing (CDC).