Reset synchronizer
Beginner
A small circuit that makes sure the chip comes out of reset in step with its clock.
Novice
A pair of flip-flops that lets reset (the signal that puts flip-flops into a known starting state) take effect immediately, but ends it only in step with the clock, so every flip-flop leaves reset on the same tick.
Expert
Asynchronous assertion, synchronous release. It keeps reset from ending too close to a clock edge, which would be a recovery or removal violation. Each asynchronous clock domain gets its own, and test logic needs a way to control its output during scan testing.
Explained in RTL design (Design Flow).
See also: Recovery and removal checks, Reset domain crossing (RDC).