Glossary

Pull-up network

Beginner

The group of switches in a gate that can connect the output to power, making it a 1.

Novice

The PMOS transistors between the supply (VDDV_{\mathrm{DD}}) and the output of a CMOS gate. When they form a conducting path, the output is pulled up to 1.

Expert

The PMOS network of a static CMOS gate, the series/parallel dual of the pull-down network. Its worst-case series depth sets PMOS sizing and rise delay.

Explained in CMOS logic (Transistors).

See also: Pull-down network, CMOS.

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