Glossary

NAND gate

Beginner

A gate whose output is 0 only when all of its inputs are 1. It means “not AND.”

Novice

NOT-AND. In CMOS, an n-input NAND has n NMOS in series to ground and n PMOS in parallel to the supply. The output falls only when every input is high.

Expert

Series NMOS stack, parallel PMOS. Logical effort (n+2)/3(n+2)/3 and parasitic delay ≈n\approx n. Preferred over NOR in planar CMOS because its series devices are the faster NMOS.

Explained in CMOS logic (Transistors).

See also: NOR gate, Transistor stack.

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