Logic synthesis
Beginner
The step where a tool turns the design code into a list of real circuit building blocks.
Novice
The step that turns RTL code into a netlist: a list of logic gates and flip-flops from a library of ready-made cells, plus the wires that connect them. Yosys is an open-source synthesis tool.
Expert
Reads the RTL, builds generic logic from it, optimizes that logic and maps it onto library cells under timing constraints. It keeps the RTL’s cycle-by-cycle behavior but may restructure everything within a cycle; equivalence checking confirms the function did not change.
Explained in RTL design (Design Flow).
See also: Register-transfer level (RTL), Netlist.