Netlist
Beginner
A list of every part in a circuit and which parts connect to which, like the wiring list for a model kit.
Novice
A list of every component in a circuit and the wires (nets) that join their pins. After synthesis each component is a standard cell from a library, and the list is written as a plain text file in the Verilog language, one line per cell.
Expert
The gate-level Verilog file that carries the design from synthesis to layout: one line per cell instance, naming the cell, the instance and what each pin connects to. Later stages edit it (test logic, buffers, the clock tree), and an equivalence check re-proves it matches the RTL after each big change.
Explained in Logic synthesis (Design Flow).
See also: Standard cell, Logical equivalence checking (LEC).