Event-driven simulation
Beginner
A way of simulating a chip that only does work when some signal actually changes.
Novice
A way of simulating a circuit that keeps a to-do list of signal changes in time order, and re-runs only the parts of the design affected by each change.
Expert
The method SystemVerilog’s meaning is defined by. Each instant of simulated time is processed in ordered phases called regions. Within a region the standard does not fix the order in which processes run, and code whose result depends on that order has a race.
Explained in RTL design (Design Flow).
See also: Cycle-based simulation, Non-blocking assignment (<=).