Non-blocking assignment (<=)
Beginner
An instruction that waits and updates all the stored values together at the clock tick, like everyone flipping their cards at once.
Novice
The <= sign. The simulator first reads every right-hand side, then updates all the left-hand sides together. That matches real flip-flops, which all take in their inputs at the same clock edge. Used for clocked logic.
Expert
The right-hand side is evaluated in the Active region and the update is queued for the NBA region later in the same time step. Because no register changes until every clocked block has read its inputs, the order in which those blocks run no longer matters.
Explained in RTL design (Design Flow).
See also: Blocking assignment (=), Event-driven simulation.