Cycle-based simulation
Beginner
A faster way to simulate a chip by computing everything once per clock tick instead of tracking every tiny change.
Novice
A faster way to simulate: compute each register’s next value once per clock tick, in an order worked out in advance, instead of tracking every small change between ticks. It cannot show delays or brief glitches.
Expert
Sorting the logic once, at compile time, in data-flow order removes most of the run-time bookkeeping of an event queue. Verilator compiles RTL into ordered C++ this way, with two-state values (0 and 1 only), evaluating logic only when its inputs may have changed.