CFET (complementary FET)
Beginner
Stacking the two kinds of transistor every logic gate needs, one directly on top of the other, to save space.
Novice
A future transistor in which an nMOS and a pMOS device are built as one stacked structure instead of side by side. That could nearly double transistor density.
Expert
n- and p-type nanosheet stacks built vertically, either monolithically (one process, one wafer) or sequentially (bonded layers). It removes n-p spacing from cell height, enabling roughly 4-track cells, but needs contacts and power from the backside for the bottom device. Demonstrated by Intel, Samsung and TSMC at IEDM 2023.
Explained in Shrinking (Transistors).
See also: Gate-all-around (GAA) nanosheet, backside power delivery.