Personal and edge devices

An edge SoC is best understood as a state machine of power modes. Each mode (deep sleep, always-on listening, music playback, full performance) has its own set of powered power domains, voltages and clocks. Every transition between modes needs four things, in order: isolation on the outputs of a domain about to go dark, so its floating signals can’t reach live logic; level shifting on signals between domains at different voltages; retention or a software reload of any state that must survive; and a power-up sequence that releases these in reverse. The savings are large, but each new domain multiplies the states and transitions that have to be verified.

The Michigan Micro Mote team describes exactly this cost. Their chips use several power domains to minimize leakage. Isolation and level conversion between them were largely manual, because tool support lagged their aggressive power gating, and as a result they often did not simulate every power state before fabrication.³

Mixed-signal coexistence. Every digital transition injects a little current into the shared silicon substrate, and that noise travels to sensitive analog and radio circuits on the same die. The standard mitigations are physical separation between noisy and sensitive blocks, careful placement of substrate contacts, guard rings and wells that collect the stray current, controlled signal transition times, and careful routing of the power lines.⁹ All of these land in the floorplan and power plan, not in the RTL, so they are decided by the physical design team rather than the logic designers.

Side channels. A chip’s power draw depends on the data it is processing, so a trace of its power over time can reveal a secret key. Differential power analysis, which averages many such traces and correlates them with guesses about the key, is practical, non-invasive and works even when the cryptography is a small fraction of the chip’s total power.¹⁰ Running the Secure Enclave on its own physically separate processor gives it built-in resistance to some software-driven side-channel attacks from the main processor, such as cache-timing attacks. Physical leakage still needs countermeasures in the crypto hardware itself, and Apple adds undisclosed ones.⁸

The leakage floor. In deep sleep almost everything is off, so standby battery life is set by the leakage of the always-on domain and of any retention supplies. Leakage rises steeply with temperature, so the cell library for that region is often chosen by its leakage at the hot corner rather than by its speed.

The power intent lives in UPF, separate from the RTL, and the same file drives both verification and implementation.² A trimmed, illustrative example for a switchable NPU domain:

# Power intent for a switchable NPU domain (IEEE 1801 style, trimmed)
create_power_domain PD_AON -include_scope
create_power_domain PD_NPU -elements {u_npu}

create_supply_net VDD_AON
create_supply_net VDD_NPU_SW

create_power_switch SW_NPU -domain PD_NPU \
  -input_supply_port  {vin  VDD_AON} \
  -output_supply_port {vout VDD_NPU_SW} \
  -control_port       {sleep npu_sleep} \
  -on_state           {on vin {!sleep}}

set_isolation ISO_NPU -domain PD_NPU -applies_to outputs \
  -clamp_value 0 -isolation_signal npu_iso -isolation_sense high

set_retention RET_NPU -domain PD_NPU \
  -save_signal {npu_save high} -restore_signal {npu_restore low}

Read it as a sequence. To power down, the controller asserts npu_save (state copied into retention latches), then npu_iso (outputs clamped), then npu_sleep (switch opens). Power-up closes the switch, waits for the rail to settle, restores the retained state (npu_restore), and only then releases npu_iso. Getting that order wrong is one of the classic bugs the flow has to catch.

Verification. Power-aware simulation reads the UPF and drives unknown values onto the outputs of any domain that is off, so a missing isolation cell shows up as a corrupted value downstream. Coverage targets include every legal power state, every transition, retention save and restore, and reset ordering. Cold boot is a special case: the Micro Mote team needed a dedicated power-on reset for its isolation network, because at cold boot even the nominally always-on signals are still rising.³ Static UPF checks, which confirm every crossing has the cell it needs without simulating anything, are rerun on the RTL, on the gate-level netlist and after place-and-route, because each step can add or move crossings.

Implementation. Each switched domain gets a voltage area (a fenced region of the floorplan), switch cells, and always-on routing for retention supplies and isolation enables. The M3 chips gave each power domain its own clock network, so the clock tree would never unexpectedly cross a domain boundary.³ Analog and RF macros get guard rings and substrate taps.⁹

Signoff. Timing is checked at every combination of operating point and corner, and the combinations multiply: $\text{DVFS points} \times \text{domain voltage combinations} \times \text{process} \times \text{temperature}$. Five operating points, two domain configurations and six process–temperature corners already make 60 timing runs. Near-threshold operating points widen the spread of gate delays, so they need variation-aware timing margins.⁴ Leakage is signed off hot, and dynamic power is checked against activity profiles recorded from real use cases.

The project’s lessons map directly onto the flow.³

• Power intent outran the tools. Isolation and level conversion between many power domains were largely manual, so not every power state was simulated before tapeout. Every unsimulated state is a scenario first exercised on silicon.
• Three spins per new block. First a large debug chip full of test points, then a form-factor chip with most debug removed, then a third spin to fix minor issues and scale production.
• Corners from the field. Chips tested only at 25 °C behaved differently implanted at 40 °C, which showed the need to design for a wider temperature range and its effect on power draw. Some 180 nm chips were light-sensitive and needed black epoxy, with a clear window over the solar cell.
• Programming and debug. The stacks are too small to attach wires to, so the team added an ultra-low-power optical receiver for programming. Once sealed, the radio is the only output, and debugging is limited by the energy budget: long sessions drain the battery deeply and shorten its life.