Yosys
Beginner
A free program that reads hardware code and turns it into a list of parts. Anyone can use it or change it.
Novice
An open-source synthesis tool. It reads Verilog, cleans up the logic and maps it onto a chip’s building blocks, using the ABC program for the final optimization and mapping. It has scripts for many FPGA families and is also used in open chip (ASIC) flows.
Expert
Open RTL synthesis framework (YosysHQ), begun by Claire Wolf. Per-family synth_* scripts infer RAM, DSP and carry primitives and call ABC (abc, abc9) for LUT mapping; output is JSON for nextpnr or BLIF/EDIF for other tools.
Explained in From hardware code to bitstream (Architectures).
See also: nextpnr, Logic synthesis.