VPR (Versatile Place and Route)
Beginner
A free research program that places and wires designs on pretend FPGAs, so scientists can test ideas for new chips.
Novice
The academic FPGA packing, placement and routing tool from the University of Toronto, part of the Verilog-to-Routing (VTR) project. It can target any FPGA described in a file, which makes it the standard tool for FPGA research.
Expert
VTR’s pack, place, route and timing engine (since 1997): a routing-resource graph built from an architecture description, annealing placement with an adaptive schedule, PathFinder-based timing-driven routing. F4PGA also uses it for real devices.
Explained in From hardware code to bitstream (Architectures).
See also: Packing (clustering), Simulated annealing, Negotiated congestion.