Timing arc
Beginner
One cause-and-effect path through a building block: when this input changes, that output changes after a certain time.
Novice
A pair of pins in a cell, such as input A to output Y, with tables for how long the output takes to respond and how sharp its edge is. A flip-flop also has arcs for its timing checks, such as setup and hold between D and CLK.
Expert
A Liberty timing() group with related_pin, timing_sense (positive_unate, negative_unate, non_unate) and timing_type (combinational, rising_edge, setup_rising, hold_rising…). STA builds its graph from these arcs plus nets, so a missing or wrong arc is a silent timing hole.
Explained in From devices to a cell library (Transistors).
See also: Liberty (.lib), NLDM (non-linear delay model).