Synchronizer (two-flop)
Beginner
Two memory cells in a row that give an unsure signal extra time to settle before the rest of the chip uses it.
Novice
Two flip-flops in a row, both on the receiving clock. The first may become undecided; the second reads it one clock tick later, by which time it has almost certainly settled.
Expert
Safe only for single-bit signals that stay steady long enough to be sampled. The settling time is one receiving-clock period minus the flops’ own delays and the wire between them, so the two flops are placed side by side. Fast clocks, low voltage or temperature extremes may call for three stages.
Explained in RTL design (Design Flow).
See also: Metastability, Clock domain crossing (CDC), MTBF (synchronizer).