Spatial (dataflow) architecture
Beginner
A chip design where many small workers sit side by side, each doing one part of the job and handing results straight to its neighbors.
Novice
A design that lays a computation out across many compute units at once, each with its own small memory, and passes data directly between them instead of sending everything through one shared memory. Contrast with CPUs and GPUs, where a central control steers many arithmetic units that all fetch from a shared memory hierarchy.
Expert
Computation is distributed in space: operators, or slices of them, are pinned to processing elements and data moves over an exposed on-chip network, usually under a schedule fixed at compile time. Covers systolic arrays, CGRAs and many-core meshes with local SRAM.
Explained in Dataflow and spatial meshes (Architectures).
See also: Processing element (PE), Network-on-chip (NoC), CGRA (coarse-grained reconfigurable array).