CGRA (coarse-grained reconfigurable array)
Beginner
A chip made of a grid of small math blocks whose connections can be rewired for each job, a middle ground between a fixed chip and a fully rewirable one.
Novice
A reconfigurable chip whose building blocks work on whole numbers (words) rather than single bits, connected by a configurable network. More efficient than an FPGA, more flexible than a fixed accelerator.
Expert
Word-level functional units and memories in a static or packet-switched interconnect, configured per kernel or per program. Avoids the bit-level routing overhead of FPGAs, at the cost of supporting only the operations and data widths its units provide.
Explained in Dataflow and spatial meshes (Architectures).
See also: FPGA, Spatial (dataflow) architecture.