Glossary

Scan flip-flop

Beginner

A tiny memory cell with an extra side door, so in test mode it can pass values along a chain.

Novice

A flip-flop with a two-way switch (a multiplexer) in front of its input. In normal mode it stores the value the logic computed; in test mode it stores the value from the previous flip-flop in the chain instead.

Expert

The mux-D style is the usual choice in standard-cell flows (two-clock LSSD styles also exist). The mux adds delay on the functional data path and the chain connection adds a load on the output; libraries offer scan versions of each flop so scan replacement is a cell swap.

Explained in Design for test (Design Flow).

See also: Scan chain, Scan enable.

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