Glossary

Scan enable

Beginner

The switch that flips the chip’s memory cells between normal work and passing test values along the chain.

Novice

A single control signal (SE) wired to every scan flip-flop. When it is 1, the flip-flops form chains and shift; when it is 0, they store what the logic computed, as in normal use.

Expert

A very high-fanout net, buffered much like a slow clock. Launch-on-capture lets it change slowly; launch-on-shift needs it to switch within one functional clock period across the whole chip, which makes it a timing-critical net.

Explained in Design for test (Design Flow).

See also: Launch-on-shift (LOS).

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