Pull-up ratio
Beginner
How strong the part of the cell that holds a 1 is compared with the door used to write into it.
Novice
In a 6T SRAM cell, the strength of a pull-up (PMOS) transistor divided by that of an access transistor. It must be small enough that the access transistor can drag a stored 1 down during a write.
Expert
, usually minimum (about 1) and kept below roughly 1.8–3. A higher PR helps read and hold stability slightly but erodes write margin, especially at slow-NMOS/fast-PMOS corners.
Explained in Memory cells (Transistors).
See also: Cell ratio (β ratio), Write margin.