Glossary

Noise margin

Beginner

How much a signal can be nudged by stray electricity before the next gate reads it wrong.

Novice

The gap between the worst output voltage a gate produces for a logic level and the worst input voltage the next gate still accepts for that level. NML=VIL−VOL\mathrm{NM}_{\mathrm{L}} = V_{\mathrm{IL}} - V_{\mathrm{OL}} and NMH=VOH−VIH\mathrm{NM}_{\mathrm{H}} = V_{\mathrm{OH}} - V_{\mathrm{IH}}.

Expert

Static noise margins taken at the unity-gain (slope −1) points of the VTC. They budget DC disturbances such as supply drop, ground bounce and coupling; dynamic noise (glitch width and energy) needs separate analysis.

Explained in CMOS logic (Transistors).

See also: Voltage transfer curve (VTC), Crosstalk (signal integrity).

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