Multi-level cell (MLC, TLC, QLC): definition

Beginner

A flash cell that stores more than one bit by using several in-between levels instead of just ‘full’ and ‘empty’.

Novice

A flash cell programmed to one of 4 (MLC, 2 bits), 8 (TLC, 3 bits) or 16 (QLC, 4 bits) threshold-voltage levels instead of 2 (SLC). More bits per cell means more capacity, but narrower windows between levels and more errors.

Expert

Each extra bit halves the voltage window per state, so programming needs more ISPP steps and verify passes, reads need more reference voltages, and retention, disturb and wear errors rise. Endurance drops with each step ( $\mathrm{SLC} \gg \mathrm{MLC} \gg \mathrm{TLC}$ ), and controllers rely on strong ECC and read-retry.