Memory consistency model
Beginner
The rules that say in what order one core’s changes to memory can appear to other cores.
Novice
The contract between hardware and software about the order in which memory operations from different cores can be observed. Sequential consistency is the strictest; x86, Arm and RISC-V allow some reordering and provide fences to stop it.
Expert
Coherence orders accesses to one location; consistency orders accesses to different locations. x86 is TSO (a load may pass an earlier store to another address); Armv8 and RISC-V RVWMO are weaker, with barriers and acquire/release accesses.