Cache coherence
Beginner
Keeping copies of the same data in different places in agreement, so no part of the chip reads a stale value.
Novice
Keeping copies of the same data in different caches in agreement. When one processor writes to an address, hardware invalidates or updates the other copies so no one reads a stale value. Each cached line carries a state, such as Modified, Shared or Invalid (the MSI protocol).
Expert
Snooping broadcasts every request to all caches, which doesn’t scale to many cores. A directory records which caches may hold each line and messages only those, which scales but costs storage and adds a hop through the directory. Accelerators are often attached without coherence, with software flushing caches before handing over data.