Glossary

Logical effort

Beginner

A score for how much harder a gate has to work than a plain inverter to do the same job.

Novice

The ratio of a gate’s input capacitance to that of an inverter that can deliver the same output current. An inverter scores 1; a NAND2 scores 4/3; a NOR2 scores 5/3.

Expert

gg in the delay model d=gh+pd = gh + p (Sutherland, Sproull and Harris). It captures the cost of the series stacks a function requires. Path effort and the best stage count follow from it, which makes it a fast way to compare gate topologies.

Explained in CMOS logic (Transistors).

See also: FO4 delay, Fan-in.

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